1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <env.h> 10#include <hang.h> 11#include <hwconfig.h> 12#include <image.h> 13#include <init.h> 14#include <net.h> 15#include <pci.h> 16#include <i2c.h> 17#include <asm/processor.h> 18#include <asm/mmu.h> 19#include <asm/cache.h> 20#include <asm/immap_85xx.h> 21#include <asm/fsl_pci.h> 22#include <fsl_ddr_sdram.h> 23#include <asm/io.h> 24#include <asm/fsl_law.h> 25#include <asm/fsl_lbc.h> 26#include <asm/mp.h> 27#include <miiphy.h> 28#include <linux/delay.h> 29#include <linux/libfdt.h> 30#include <fdt_support.h> 31#include <fsl_mdio.h> 32#include <tsec.h> 33#include <vsc7385.h> 34#include <ioports.h> 35#include <asm/fsl_serdes.h> 36#include <netdev.h> 37 38#ifdef CONFIG_QE 39 40#define GPIO_GETH_SW_PORT 1 41#define GPIO_GETH_SW_PIN 29 42#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN)) 43 44#define GPIO_SLIC_PORT 1 45#define GPIO_SLIC_PIN 30 46#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) 47 48const qe_iop_conf_t qe_iop_conf_tab[] = { 49 /* GPIO */ 50 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ 51 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ 52 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ 53 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ 54 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 55}; 56#endif 57 58struct cpld_data { 59 u8 cpld_rev_major; 60 u8 pcba_rev; 61 u8 wd_cfg; 62 u8 rst_bps_sw; 63 u8 load_default_n; 64 u8 rst_bps_wd; 65 u8 bypass_enable; 66 u8 bps_led; 67 u8 status_led; /* offset: 0x8 */ 68 u8 fxo_led; /* offset: 0x9 */ 69 u8 fxs_led; /* offset: 0xa */ 70 u8 rev4[2]; 71 u8 system_rst; /* offset: 0xd */ 72 u8 bps_out; 73 u8 rev5[3]; 74 u8 cpld_rev_minor; 75}; 76 77#define CPLD_WD_CFG 0x03 78#define CPLD_RST_BSW 0x00 79#define CPLD_RST_BWD 0x00 80#define CPLD_BYPASS_EN 0x03 81#define CPLD_STATUS_LED 0x01 82#define CPLD_FXO_LED 0x01 83#define CPLD_FXS_LED 0x0F 84#define CPLD_SYS_RST 0x00 85 86void board_reset_prepare(void) 87{ 88 /* 89 * During reset preparation, turn off external watchdog. 90 * This ensures that external watchdog does not trigger 91 * another reset or possible infinite reset loop. 92 */ 93 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 94 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); 95 in_8(&cpld_data->wd_cfg); /* Read back to sync write */ 96} 97 98void board_reset_last(void) 99{ 100 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 101 out_8(&cpld_data->system_rst, 1); 102} 103 104void board_cpld_init(void) 105{ 106 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 107 u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); 108 109 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); 110 out_8(&cpld_data->status_led, CPLD_STATUS_LED); 111 out_8(&cpld_data->fxo_led, CPLD_FXO_LED); 112 out_8(&cpld_data->fxs_led, CPLD_FXS_LED); 113 114 /* 115 * CPLD's system reset register on P1/P2 RDB boards is not autocleared 116 * after flipping it. If this register is set to one then CPLD triggers 117 * reset of CPU in few ms. 118 * 119 * CPLD does not trigger reset of CPU for 100ms after the last reset. 120 * 121 * This means that trying to reset board via CPLD system reset register 122 * cause reboot loop. To prevent this reboot loop, the only workaround 123 * is to try to clear CPLD's system reset register as early as possible 124 * and it has to be done in 100ms since the last start of reset. 125 */ 126 out_8(&cpld_data->system_rst, CPLD_SYS_RST); 127 128 /* 129 * If watchdog timer was already set to non-disabled value then it means 130 * that watchdog timer was already activated, has already expired and 131 * caused CPU reset. If this happened then due to CPLD firmware bug, 132 * writing to wd_cfg register has no effect and therefore it is not 133 * possible to reactivate watchdog timer again. Also if CPU was reset 134 * via watchdog then some peripherals like i2c do not work. Watchdog and 135 * i2c start working again after CPU reset via non-watchdog method. 136 * 137 * So in case watchdog timer register in CPLD was already enabled then 138 * disable it in CPLD and reset CPU which cause new boot. Watchdog timer 139 * is disabled few lines above, after reading CPLD previous value. 140 * This logic (disabling timer before reset) prevents reboot loop. 141 */ 142 if (prev_wd_cfg != CPLD_WD_CFG) { 143 eieio(); 144 do_reset(NULL, 0, 0, NULL); 145 while (1); /* do_reset() does not occur immediately */ 146 } 147} 148 149void board_gpio_init(void) 150{ 151#ifdef CONFIG_QE 152 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 153 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); 154 155 /* Enable VSC7385 switch */ 156 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); 157 158 /* Enable SLIC */ 159 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); 160#else 161 162 ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); 163 164 /* 165 * GPIO10 DDR Reset, open drain 166 * GPIO7 LOAD_DEFAULT_N Input 167 * GPIO11 WDI (watchdog input) 168 * GPIO12 Ethernet Switch Reset 169 * GPIO13 SLIC Reset 170 */ 171 172 setbits_be32(&pgpio->gpdir, 0x02130000); 173#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) 174 /* init DDR3 reset signal */ 175 setbits_be32(&pgpio->gpdir, 0x00200000); 176 setbits_be32(&pgpio->gpodr, 0x00200000); 177 clrbits_be32(&pgpio->gpdat, 0x00200000); 178 udelay(1000); 179 setbits_be32(&pgpio->gpdat, 0x00200000); 180 udelay(1000); 181 clrbits_be32(&pgpio->gpdir, 0x00200000); 182#endif 183 184#ifdef CONFIG_VSC7385_ENET 185 /* reset VSC7385 Switch */ 186 setbits_be32(&pgpio->gpdir, 0x00080000); 187 setbits_be32(&pgpio->gpdat, 0x00080000); 188#endif 189 190#ifdef CFG_SLIC 191 /* reset SLIC */ 192 setbits_be32(&pgpio->gpdir, 0x00040000); 193 setbits_be32(&pgpio->gpdat, 0x00040000); 194#endif 195#endif 196} 197 198int board_early_init_f(void) 199{ 200 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 201 202 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); 203#ifndef SDHC_WP_IS_GPIO 204 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP); 205#endif 206 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); 207 208 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 209#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) 210 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); 211#endif 212 213 board_gpio_init(); 214 board_cpld_init(); 215 216 return 0; 217} 218 219#if defined(CONFIG_TARGET_P1020RDB_PC) 220#define BOARD_NAME "P1020RDB-PC" 221#elif defined(CONFIG_TARGET_P1020RDB_PD) 222#define BOARD_NAME "P1020RDB-PD" 223#elif defined(CONFIG_TARGET_P2020RDB) 224#define BOARD_NAME "P2020RDB-PC" 225#endif 226 227int checkboard(void) 228{ 229 struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); 230 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 231 u8 in, out, invert, io_config, val; 232 int bus_num = CONFIG_SYS_SPD_BUS_NUM; 233 234 /* FIXME: This should just use the model from the device tree or similar */ 235#ifdef BOARD_NAME 236 printf("Board: %s ", BOARD_NAME); 237#endif 238 239 printf("CPLD: V%d.%d PCBA: V%d.0\n", 240 in_8(&cpld_data->cpld_rev_major) & 0x0F, 241 in_8(&cpld_data->cpld_rev_minor) & 0x0F, 242 in_8(&cpld_data->pcba_rev) & 0x0F); 243 244 /* Initialize i2c early for rom_loc and flash bank information */ 245 #if CONFIG_IS_ENABLED(DM_I2C) 246 struct udevice *dev; 247 int ret; 248 249 ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR, 250 1, &dev); 251 if (ret) { 252 printf("%s: Cannot find udev for a bus %d\n", __func__, 253 bus_num); 254 return 0; /* Don't want to hang() on this error */ 255 } 256 257 if (dm_i2c_read(dev, 0, &in, 1) < 0 || 258 dm_i2c_read(dev, 1, &out, 1) < 0 || 259 dm_i2c_read(dev, 2, &invert, 1) < 0 || 260 dm_i2c_read(dev, 3, &io_config, 1) < 0) { 261 printf("Error reading i2c boot information!\n"); 262 return 0; /* Don't want to hang() on this error */ 263 } 264 #else /* Non DM I2C support - will be removed */ 265 i2c_set_bus_num(bus_num); 266 267 if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || 268 i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || 269 i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || 270 i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { 271 printf("Error reading i2c boot information!\n"); 272 return 0; /* Don't want to hang() on this error */ 273 } 274 #endif 275 276 val = ((in ^ invert) & io_config) | (out & (~io_config)); 277 278 puts("rom_loc: "); 279 if (0) { 280#ifdef __SW_BOOT_SD 281 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { 282 puts("sd"); 283#endif 284#ifdef __SW_BOOT_SD2 285 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { 286 puts("sd"); 287#endif 288#ifdef __SW_BOOT_SPI 289 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { 290 puts("spi"); 291#endif 292#ifdef __SW_BOOT_NAND 293 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) { 294 puts("nand"); 295#endif 296#ifdef __SW_BOOT_PCIE 297 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) { 298 puts("pcie"); 299#endif 300 } else { 301 if (val & 0x2) 302 puts("nor lower bank"); 303 else 304 puts("nor upper bank"); 305 } 306 puts("\n"); 307 308 if (val & 0x1) { 309 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 310 puts("SD/MMC : 8-bit Mode\n"); 311 puts("eSPI : Disabled\n"); 312 } else { 313 puts("SD/MMC : 4-bit Mode\n"); 314 puts("eSPI : Enabled\n"); 315 } 316 317 return 0; 318} 319 320int board_early_init_r(void) 321{ 322 const unsigned int flashbase = CFG_SYS_FLASH_BASE; 323 int flash_esel = find_tlb_idx((void *)flashbase, 1); 324#ifdef CONFIG_VSC7385_ENET 325 unsigned int vscfw_addr; 326 char *tmp; 327#endif 328 329 /* 330 * Remap Boot flash region to caching-inhibited 331 * so that flash can be erased properly. 332 */ 333 334 /* Flush d-cache and invalidate i-cache of any FLASH data */ 335 flush_dcache(); 336 invalidate_icache(); 337 338 if (flash_esel == -1) { 339 /* very unlikely unless something is messed up */ 340 puts("Error: Could not find TLB for FLASH BASE\n"); 341 flash_esel = 2; /* give our best effort to continue */ 342 } else { 343 /* invalidate existing TLB entry for flash */ 344 disable_tlb(flash_esel); 345 } 346 347 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 348 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 349 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ 350 351#ifdef CONFIG_VSC7385_ENET 352 /* If a VSC7385 microcode image is present, then upload it. */ 353 tmp = env_get("vscfw_addr"); 354 if (tmp) { 355 vscfw_addr = hextoul(tmp, NULL); 356 printf("uploading VSC7385 microcode from %x\n", vscfw_addr); 357 if (vsc7385_upload_firmware((void *)vscfw_addr, 358 CFG_VSC7385_IMAGE_SIZE)) 359 puts("Failure uploading VSC7385 microcode.\n"); 360 } else { 361 puts("No address specified for VSC7385 microcode.\n"); 362 } 363#endif 364 return 0; 365} 366 367#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP) 368static void fix_max6370_watchdog(void *blob) 369{ 370 int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370"); 371 ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); 372 u32 gpioval = in_be32(&pgpio->gpdat); 373 374 /* 375 * Delete watchdog max6370 node in load_default mode (detected by 376 * GPIO7 - LOAD_DEFAULT_N) because CPLD in load_default mode ignores 377 * watchdog reset signal. CPLD in load_default mode does not reset 378 * board when watchdog triggers reset signal. 379 */ 380 if (!(gpioval & BIT(31-7)) && off >= 0) 381 fdt_del_node(blob, off); 382} 383#endif 384 385#ifdef CONFIG_OF_BOARD_SETUP 386int ft_board_setup(void *blob, struct bd_info *bd) 387{ 388 phys_addr_t base; 389 phys_size_t size; 390#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) 391 const char *soc_usb_compat = "fsl-usb2-dr"; 392 int usb_err, usb1_off, usb2_off; 393#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 394 int err; 395#endif 396#endif 397 398 ft_cpu_setup(blob, bd); 399 400 base = env_get_bootm_low(); 401 size = env_get_bootm_size(); 402 403 fdt_fixup_memory(blob, (u64)base, (u64)size); 404 405#ifdef CONFIG_QE 406 do_fixup_by_compat(blob, "fsl,qe", "status", "okay", 407 sizeof("okay"), 0); 408#endif 409 410 fix_max6370_watchdog(blob); 411 412#if defined(CONFIG_HAS_FSL_DR_USB) 413 fsl_fdt_fixup_dr_usb(blob, bd); 414#endif 415 416#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) 417#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 418 /* Delete eLBC node as it is muxed with USB2 controller */ 419 if (hwconfig("usb2")) { 420 const char *soc_elbc_compat = "fsl,p1020-elbc"; 421 int off = fdt_node_offset_by_compatible(blob, -1, 422 soc_elbc_compat); 423 if (off < 0) { 424 printf("WARNING: could not find compatible node %s\n", 425 soc_elbc_compat); 426 return off; 427 } 428 err = fdt_del_node(blob, off); 429 if (err < 0) { 430 printf("WARNING: could not remove %s\n", 431 soc_elbc_compat); 432 return err; 433 } 434 return 0; 435 } 436#endif 437 438/* Delete USB2 node as it is muxed with eLBC */ 439 usb1_off = fdt_node_offset_by_compatible(blob, -1, 440 soc_usb_compat); 441 if (usb1_off < 0) { 442 printf("WARNING: could not find compatible node %s\n", 443 soc_usb_compat); 444 return usb1_off; 445 } 446 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, 447 soc_usb_compat); 448 if (usb2_off < 0) { 449 printf("WARNING: could not find compatible node %s\n", 450 soc_usb_compat); 451 return usb2_off; 452 } 453 usb_err = fdt_del_node(blob, usb2_off); 454 if (usb_err < 0) { 455 printf("WARNING: could not remove %s\n", soc_usb_compat); 456 return usb_err; 457 } 458#endif 459 460 return 0; 461} 462#endif 463 464#ifdef CONFIG_OF_BOARD_FIXUP 465int board_fix_fdt(void *blob) 466{ 467 fix_max6370_watchdog(blob); 468 return 0; 469} 470#endif 471