1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 */ 5 6#include <config.h> 7 8/* image version */ 9 10IMAGE_VERSION 2 11 12/* 13 * Boot Device : one of 14 * spi/sd/nand/onenand, qspi/nor 15 */ 16 17BOOT_FROM sd 18 19/* 20 * Device Configuration Data (DCD) 21 * 22 * Each entry must have the format: 23 * Addr-type Address Value 24 * 25 * where: 26 * Addr-type register length (1,2 or 4 bytes) 27 * Address absolute address of the register 28 * value value to be stored in the register 29 */ 30 31/* Enable all clocks */ 32DATA 4 0x020c4068 0xffffffff 33DATA 4 0x020c406c 0xffffffff 34DATA 4 0x020c4070 0xffffffff 35DATA 4 0x020c4074 0xffffffff 36DATA 4 0x020c4078 0xffffffff 37DATA 4 0x020c407c 0xffffffff 38DATA 4 0x020c4080 0xffffffff 39DATA 4 0x020c4084 0xffffffff 40 41/* IOMUX - DDR IO Type */ 42DATA 4 0x020e0618 0x000c0000 43DATA 4 0x020e05fc 0x00000000 44 45/* Clock */ 46DATA 4 0x020e032c 0x00000030 47 48/* Address */ 49DATA 4 0x020e0300 0x00000030 50DATA 4 0x020e02fc 0x00000030 51DATA 4 0x020e05f4 0x00000030 52 53/* Control */ 54DATA 4 0x020e0340 0x00000030 55 56DATA 4 0x020e0320 0x00000000 57DATA 4 0x020e0310 0x00000030 58DATA 4 0x020e0314 0x00000030 59DATA 4 0x020e0614 0x00000030 60 61/* Data Strobe */ 62DATA 4 0x020e05f8 0x00020000 63DATA 4 0x020e0330 0x00000030 64DATA 4 0x020e0334 0x00000030 65DATA 4 0x020e0338 0x00000030 66DATA 4 0x020e033c 0x00000030 67 68/* Data */ 69DATA 4 0x020e0608 0x00020000 70DATA 4 0x020e060c 0x00000030 71DATA 4 0x020e0610 0x00000030 72DATA 4 0x020e061c 0x00000030 73DATA 4 0x020e0620 0x00000030 74DATA 4 0x020e02ec 0x00000030 75DATA 4 0x020e02f0 0x00000030 76DATA 4 0x020e02f4 0x00000030 77DATA 4 0x020e02f8 0x00000030 78 79/* Calibrations - ZQ */ 80DATA 4 0x021b0800 0xa1390003 81 82/* Write leveling */ 83DATA 4 0x021b080c 0x002C003D 84DATA 4 0x021b0810 0x00110046 85 86/* DQS Read Gate */ 87DATA 4 0x021b083c 0x4160016C 88DATA 4 0x021b0840 0x013C016C 89 90/* Read/Write Delay */ 91DATA 4 0x021b0848 0x46424446 92DATA 4 0x021b0850 0x3A3C3C3A 93 94DATA 4 0x021b08c0 0x2492244A 95 96/* read data bit delay */ 97DATA 4 0x021b081c 0x33333333 98DATA 4 0x021b0820 0x33333333 99DATA 4 0x021b0824 0x33333333 100DATA 4 0x021b0828 0x33333333 101 102/* Complete calibration by forced measurement */ 103DATA 4 0x021b08b8 0x00000800 104 105/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 106DATA 4 0x021b0004 0x0002002d 107DATA 4 0x021b0008 0x00333030 108DATA 4 0x021b000c 0x676b52f3 109DATA 4 0x021b0010 0xb66d8b63 110DATA 4 0x021b0014 0x01ff00db 111DATA 4 0x021b0018 0x00011740 112DATA 4 0x021b001c 0x00008000 113DATA 4 0x021b002c 0x000026d2 114DATA 4 0x021b0030 0x006b1023 115DATA 4 0x021b0040 0x0000007f 116DATA 4 0x021b0000 0x85190000 117 118/* Initialize MT41K256M16HA-125 - MR2 */ 119DATA 4 0x021b001c 0x04008032 120/* MR3 */ 121DATA 4 0x021b001c 0x00008033 122/* MR1 */ 123DATA 4 0x021b001c 0x00068031 124/* MR0 */ 125DATA 4 0x021b001c 0x05208030 126/* DDR device ZQ calibration */ 127DATA 4 0x021b001c 0x04008040 128 129/* Final DDR setup, before operation start */ 130DATA 4 0x021b0020 0x00000800 131DATA 4 0x021b0818 0x00022227 132DATA 4 0x021b0004 0x0002556d 133DATA 4 0x021b0404 0x00011006 134DATA 4 0x021b001c 0x00000000 135