1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8#include <init.h>
9#include <net.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/iomux.h>
12#include <asm/arch/crm_regs.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/mx6-ddr.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/global_data.h>
18#include <asm/gpio.h>
19#include <asm/mach-imx/iomux-v3.h>
20#include <asm/mach-imx/mxc_i2c.h>
21#include <asm/io.h>
22#include <asm/sections.h>
23#include <linux/sizes.h>
24#include <common.h>
25#include <fsl_esdhc_imx.h>
26#include <i2c.h>
27#include <mmc.h>
28#include <power/pmic.h>
29#include <power/pfuze100_pmic.h>
30#include "../common/pfuze.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
35	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
36	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37
38#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
39	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
40	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41
42#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
43	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
44	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
45
46#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
47			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
48			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
49			PAD_CTL_SRE_FAST)
50
51#define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)
52
53int dram_init(void)
54{
55	gd->ram_size = imx_ddr_size();
56
57	return 0;
58}
59
60static iomux_v3_cfg_t const uart1_pads[] = {
61	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
62	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
63};
64
65#ifdef CONFIG_SPL_BUILD
66static iomux_v3_cfg_t const usdhc1_pads[] = {
67	/* 8 bit SD */
68	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74	MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75	MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76	MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77	MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78
79	/*CD pin*/
80	MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
81};
82
83static iomux_v3_cfg_t const usdhc2_pads[] = {
84	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90
91	/*CD pin*/
92	MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
93};
94
95static iomux_v3_cfg_t const usdhc3_pads[] = {
96	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102
103	/*CD pin*/
104	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
105};
106#endif
107
108static void setup_iomux_uart(void)
109{
110	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
111}
112
113int board_mmc_get_env_dev(int devno)
114{
115	return devno;
116}
117
118#ifdef CONFIG_DM_PMIC_PFUZE100
119int power_init_board(void)
120{
121	struct udevice *dev;
122	int ret;
123	u32 dev_id, rev_id, i;
124	u32 switch_num = 6;
125	u32 offset = PFUZE100_SW1CMODE;
126
127	ret = pmic_get("pfuze100@08", &dev);
128	if (ret == -ENODEV)
129		return 0;
130
131	if (ret != 0)
132		return ret;
133
134	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
135	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
136	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
137
138	/* set SW1AB staby volatage 0.975V */
139	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
140
141	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
142	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
143
144	/* set SW1C staby volatage 0.975V */
145	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
146
147	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
148	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
149
150	/* Init mode to APS_PFM */
151	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
152
153	for (i = 0; i < switch_num - 1; i++)
154		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
155
156	return 0;
157}
158#endif
159
160#ifdef CONFIG_FEC_MXC
161
162static int setup_fec(void)
163{
164	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
165
166	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
167	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
168
169	return enable_fec_anatop_clock(0, ENET_50MHZ);
170}
171#endif
172
173int board_early_init_f(void)
174{
175	setup_iomux_uart();
176
177	return 0;
178}
179
180int board_init(void)
181{
182	/* address of boot parameters */
183	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
184
185#ifdef	CONFIG_FEC_MXC
186	setup_fec();
187#endif
188
189	return 0;
190}
191
192int checkboard(void)
193{
194	puts("Board: MX6SLEVK\n");
195
196	return 0;
197}
198
199#ifdef CONFIG_SPL_BUILD
200#include <spl.h>
201#include <linux/libfdt.h>
202
203#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
204#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
205#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
206
207static struct fsl_esdhc_cfg usdhc_cfg[3] = {
208	{USDHC1_BASE_ADDR},
209	{USDHC2_BASE_ADDR, 0, 4},
210	{USDHC3_BASE_ADDR, 0, 4},
211};
212
213int board_mmc_getcd(struct mmc *mmc)
214{
215	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
216	int ret = 0;
217
218	switch (cfg->esdhc_base) {
219	case USDHC1_BASE_ADDR:
220		gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
221		ret = !gpio_get_value(USDHC1_CD_GPIO);
222		break;
223	case USDHC2_BASE_ADDR:
224		gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
225		ret = !gpio_get_value(USDHC2_CD_GPIO);
226		break;
227	case USDHC3_BASE_ADDR:
228		gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
229		ret = !gpio_get_value(USDHC3_CD_GPIO);
230		break;
231	}
232
233	return ret;
234}
235
236int board_mmc_init(struct bd_info *bis)
237{
238	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
239	u32 val;
240	u32 port;
241
242	val = readl(&src_regs->sbmr1);
243
244	/* Boot from USDHC */
245	port = (val >> 11) & 0x3;
246	switch (port) {
247	case 0:
248		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
249						 ARRAY_SIZE(usdhc1_pads));
250		gpio_direction_input(USDHC1_CD_GPIO);
251		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
252		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
253		break;
254	case 1:
255		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
256						 ARRAY_SIZE(usdhc2_pads));
257		gpio_direction_input(USDHC2_CD_GPIO);
258		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
259		usdhc_cfg[0].max_bus_width = 4;
260		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
261		break;
262	case 2:
263		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
264						 ARRAY_SIZE(usdhc3_pads));
265		gpio_direction_input(USDHC3_CD_GPIO);
266		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
267		usdhc_cfg[0].max_bus_width = 4;
268		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
269		break;
270	}
271
272	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
273	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
274}
275
276const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
277	.dram_sdqs0 = 0x00003030,
278	.dram_sdqs1 = 0x00003030,
279	.dram_sdqs2 = 0x00003030,
280	.dram_sdqs3 = 0x00003030,
281	.dram_dqm0 = 0x00000030,
282	.dram_dqm1 = 0x00000030,
283	.dram_dqm2 = 0x00000030,
284	.dram_dqm3 = 0x00000030,
285	.dram_cas  = 0x00000030,
286	.dram_ras  = 0x00000030,
287	.dram_sdclk_0 = 0x00000028,
288	.dram_reset = 0x00000030,
289	.dram_sdba2 = 0x00000000,
290	.dram_odt0 = 0x00000008,
291	.dram_odt1 = 0x00000008,
292};
293
294const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
295	.grp_b0ds = 0x00000030,
296	.grp_b1ds = 0x00000030,
297	.grp_b2ds = 0x00000030,
298	.grp_b3ds = 0x00000030,
299	.grp_addds = 0x00000030,
300	.grp_ctlds = 0x00000030,
301	.grp_ddrmode_ctl = 0x00020000,
302	.grp_ddrpke = 0x00000000,
303	.grp_ddrmode = 0x00020000,
304	.grp_ddr_type = 0x00080000,
305};
306
307const struct mx6_mmdc_calibration mx6_mmcd_calib = {
308	.p0_mpdgctrl0 =  0x20000000,
309	.p0_mpdgctrl1 =  0x00000000,
310	.p0_mprddlctl =  0x4241444a,
311	.p0_mpwrdlctl =  0x3030312b,
312	.mpzqlp2ctl = 0x1b4700c7,
313};
314
315static struct mx6_lpddr2_cfg mem_ddr = {
316	.mem_speed = 800,
317	.density = 4,
318	.width = 32,
319	.banks = 8,
320	.rowaddr = 14,
321	.coladdr = 10,
322	.trcd_lp = 2000,
323	.trppb_lp = 2000,
324	.trpab_lp = 2250,
325	.trasmin = 4200,
326};
327
328static void ccgr_init(void)
329{
330	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
331
332	writel(0xFFFFFFFF, &ccm->CCGR0);
333	writel(0xFFFFFFFF, &ccm->CCGR1);
334	writel(0xFFFFFFFF, &ccm->CCGR2);
335	writel(0xFFFFFFFF, &ccm->CCGR3);
336	writel(0xFFFFFFFF, &ccm->CCGR4);
337	writel(0xFFFFFFFF, &ccm->CCGR5);
338	writel(0xFFFFFFFF, &ccm->CCGR6);
339
340	writel(0x00260324, &ccm->cbcmr);
341}
342
343static void spl_dram_init(void)
344{
345	struct mx6_ddr_sysinfo sysinfo = {
346		.dsize = mem_ddr.width / 32,
347		.cs_density = 20,
348		.ncs = 2,
349		.cs1_mirror = 0,
350		.walat = 0,
351		.ralat = 2,
352		.mif3_mode = 3,
353		.bi_on = 1,
354		.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
355		.rtt_nom = 0,
356		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
357		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
358		.ddr_type = DDR_TYPE_LPDDR2,
359		.refsel = 0,	/* Refresh cycles at 64KHz */
360		.refr = 3,	/* 4 refresh commands per refresh cycle */
361	};
362	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
363	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
364}
365
366void board_init_f(ulong dummy)
367{
368	/* setup AIPS and disable watchdog */
369	arch_cpu_init();
370
371	ccgr_init();
372
373	/* iomux and setup of i2c */
374	board_early_init_f();
375
376	/* setup GP timer */
377	timer_init();
378
379	/* UART clocks enabled and gd valid - init serial console */
380	preloader_console_init();
381
382	/* DDR initialization */
383	spl_dram_init();
384
385	/* Clear the BSS. */
386	memset(__bss_start, 0, __bss_end - __bss_start);
387
388	/* load/boot image from boot device */
389	board_init_r(NULL, 0);
390}
391#endif
392