1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 */
9
10#include <config.h>
11#include <common.h>
12#include <asm/io.h>
13#include <asm/immap.h>
14
15#if defined(CONFIG_CMD_NAND)
16#include <nand.h>
17#include <linux/mtd/mtd.h>
18#include <linux/mtd/rawnand.h>
19
20#define SET_CLE		0x10
21#define SET_ALE		0x08
22
23static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
24{
25	struct nand_chip *this = mtd_to_nand(mtdinfo);
26	volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
27
28	if (ctrl & NAND_CTRL_CHANGE) {
29		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
30
31		IO_ADDR_W &= ~(SET_ALE | SET_CLE);
32
33		if (ctrl & NAND_NCE)
34			*nCE &= 0xFFFB;
35		else
36			*nCE |= 0x0004;
37
38		if (ctrl & NAND_CLE)
39			IO_ADDR_W |= SET_CLE;
40		if (ctrl & NAND_ALE)
41			IO_ADDR_W |= SET_ALE;
42
43		this->IO_ADDR_W = (void *)IO_ADDR_W;
44
45	}
46
47	if (cmd != NAND_CMD_NONE)
48		writeb(cmd, this->IO_ADDR_W);
49}
50
51int board_nand_init(struct nand_chip *nand)
52{
53	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
54	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
55
56	clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
57
58	/*
59	 * set up pin configuration - enabled 2nd output buffer's signals
60	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
61	 * to use nCE signal
62	 */
63	clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
64	setbits_8(&gpio->pddr_timer, 0x08);
65	setbits_8(&gpio->ppd_timer, 0x08);
66	out_8(&gpio->pclrr_timer, 0);
67	out_8(&gpio->podr_timer, 0);
68
69	nand->chip_delay = 60;
70	nand->ecc.mode = NAND_ECC_SOFT;
71	nand->cmd_ctrl = nand_hwcontrol;
72
73	return 0;
74}
75#endif
76