1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2004 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <init.h> 10#include <malloc.h> 11#include <asm/global_data.h> 12#include <asm/immap.h> 13#include <linux/delay.h> 14 15DECLARE_GLOBAL_DATA_PTR; 16 17int checkboard (void) { 18 ulong val; 19 uchar val8; 20 21 puts ("Board: "); 22 puts("Freescale M5249EVB"); 23 val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; 24 printf(" (Switch=%1X)\n", val8); 25 26 /* 27 * Set LED on 28 */ 29 val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED; 30 mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ 31 32 return 0; 33}; 34 35 36int dram_init(void) 37{ 38 unsigned long junk = 0xa5a59696; 39 40 /* 41 * Note: 42 * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 43 */ 44 45#ifdef CFG_SYS_FAST_CLK 46 /* 47 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) 48 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 49 */ 50 mbar_writeShort(MCFSIM_DCR, 0x8239); 51#elif CFG_SYS_PLL_BYPASS 52 /* 53 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) 54 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 55 */ 56 mbar_writeShort(MCFSIM_DCR, 0x8202); 57#else 58 /* 59 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) 60 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) 61 */ 62 mbar_writeShort(MCFSIM_DCR, 0x8222); 63#endif 64 65 /* 66 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), 67 * PM=1 (continuous page mode) 68 */ 69 70 /* RE=0 (keep auto-refresh disabled while setting up registers) */ 71 mbar_writeLong(MCFSIM_DACR0, 0x00003324); 72 73 /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ 74 mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); 75 76 /** Precharge sequence **/ 77 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ 78 *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ 79 udelay(0x10); /* Allow several Precharge cycles */ 80 81 /** Refresh Sequence **/ 82 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ 83 udelay(0x7d0); /* Allow gobs of refresh cycles */ 84 85 /** Mode Register initialization **/ 86 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ 87 *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ 88 89 gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; 90 91 return 0; 92}; 93 94 95int testdram(void) 96{ 97 /* TODO: XXX XXX XXX */ 98 printf ("DRAM test not implemented!\n"); 99 100 return (0); 101} 102