1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2021-2022 NXP
5 */
6
7#include <i2c.h>
8#include <init.h>
9#include <asm/global_data.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/soc.h>
14#include <asm/arch-fsl-layerscape/fsl_icid.h>
15#include <fdt_support.h>
16#include <hwconfig.h>
17#include <ahci.h>
18#include <mmc.h>
19#include <scsi.h>
20#include <fm_eth.h>
21#include <fsl_esdhc.h>
22#include <fsl_ifc.h>
23#include "cpld.h"
24#ifdef CONFIG_U_QE
25#include <fsl_qe.h>
26#endif
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#ifdef CONFIG_TFABOOT
31struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
32	{
33		"nor",
34		CFG_SYS_NOR_CSPR,
35		CFG_SYS_NOR_CSPR_EXT,
36		CFG_SYS_NOR_AMASK,
37		CFG_SYS_NOR_CSOR,
38		{
39			CFG_SYS_NOR_FTIM0,
40			CFG_SYS_NOR_FTIM1,
41			CFG_SYS_NOR_FTIM2,
42			CFG_SYS_NOR_FTIM3
43		},
44
45	},
46	{
47		"nand",
48		CFG_SYS_NAND_CSPR,
49		CFG_SYS_NAND_CSPR_EXT,
50		CFG_SYS_NAND_AMASK,
51		CFG_SYS_NAND_CSOR,
52		{
53			CFG_SYS_NAND_FTIM0,
54			CFG_SYS_NAND_FTIM1,
55			CFG_SYS_NAND_FTIM2,
56			CFG_SYS_NAND_FTIM3
57		},
58	},
59	{
60		"cpld",
61		CFG_SYS_CPLD_CSPR,
62		CFG_SYS_CPLD_CSPR_EXT,
63		CFG_SYS_CPLD_AMASK,
64		CFG_SYS_CPLD_CSOR,
65		{
66			CFG_SYS_CPLD_FTIM0,
67			CFG_SYS_CPLD_FTIM1,
68			CFG_SYS_CPLD_FTIM2,
69			CFG_SYS_CPLD_FTIM3
70		},
71	}
72};
73
74struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
75	{
76		"nand",
77		CFG_SYS_NAND_CSPR,
78		CFG_SYS_NAND_CSPR_EXT,
79		CFG_SYS_NAND_AMASK,
80		CFG_SYS_NAND_CSOR,
81		{
82			CFG_SYS_NAND_FTIM0,
83			CFG_SYS_NAND_FTIM1,
84			CFG_SYS_NAND_FTIM2,
85			CFG_SYS_NAND_FTIM3
86		},
87	},
88	{
89		"nor",
90		CFG_SYS_NOR_CSPR,
91		CFG_SYS_NOR_CSPR_EXT,
92		CFG_SYS_NOR_AMASK,
93		CFG_SYS_NOR_CSOR,
94		{
95			CFG_SYS_NOR_FTIM0,
96			CFG_SYS_NOR_FTIM1,
97			CFG_SYS_NOR_FTIM2,
98			CFG_SYS_NOR_FTIM3
99		},
100	},
101	{
102		"cpld",
103		CFG_SYS_CPLD_CSPR,
104		CFG_SYS_CPLD_CSPR_EXT,
105		CFG_SYS_CPLD_AMASK,
106		CFG_SYS_CPLD_CSOR,
107		{
108			CFG_SYS_CPLD_FTIM0,
109			CFG_SYS_CPLD_FTIM1,
110			CFG_SYS_CPLD_FTIM2,
111			CFG_SYS_CPLD_FTIM3
112		},
113	}
114};
115
116void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
117{
118	enum boot_src src = get_boot_src();
119
120	if (src == BOOT_SOURCE_IFC_NAND)
121		regs_info->regs = ifc_cfg_nand_boot;
122	else
123		regs_info->regs = ifc_cfg_nor_boot;
124	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
125}
126
127#endif
128int board_early_init_f(void)
129{
130	fsl_lsch2_early_init_f();
131
132	return 0;
133}
134
135#ifndef CONFIG_SPL_BUILD
136
137int checkboard(void)
138{
139#ifdef CONFIG_TFABOOT
140	enum boot_src src = get_boot_src();
141#endif
142	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
143#ifndef CONFIG_SD_BOOT
144	u8 cfg_rcw_src1, cfg_rcw_src2;
145	u16 cfg_rcw_src;
146#endif
147	u8 sd1refclk_sel;
148
149	printf("Board: LS1043ARDB, boot from ");
150
151#ifdef CONFIG_TFABOOT
152	if (src == BOOT_SOURCE_SD_MMC)
153		puts("SD\n");
154	else {
155#endif
156
157#ifdef CONFIG_SD_BOOT
158	puts("SD\n");
159#else
160	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
161	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
162	cpld_rev_bit(&cfg_rcw_src1);
163	cfg_rcw_src = cfg_rcw_src1;
164	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
165
166	if (cfg_rcw_src == 0x25)
167		printf("vBank %d\n", CPLD_READ(vbank));
168	else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118))
169		puts("NAND\n");
170	else
171		printf("Invalid setting of SW4\n");
172#endif
173
174#ifdef CONFIG_TFABOOT
175	}
176#endif
177	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
178	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
179
180	puts("SERDES Reference Clocks:\n");
181	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
182	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
183
184	return 0;
185}
186
187int board_init(void)
188{
189	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
190
191#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
192	erratum_a010315();
193#endif
194
195#ifdef CONFIG_FSL_IFC
196	init_final_memctl_regs();
197#endif
198
199#ifdef CONFIG_NXP_ESBC
200	/* In case of Secure Boot, the IBR configures the SMMU
201	 * to allow only Secure transactions.
202	 * SMMU must be reset in bypass mode.
203	 * Set the ClientPD bit and Clear the USFCFG Bit
204	 */
205	u32 val;
206	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
207	out_le32(SMMU_SCR0, val);
208	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
209	out_le32(SMMU_NSCR0, val);
210#endif
211
212#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
213	pci_init();
214#endif
215
216#ifdef CONFIG_U_QE
217	u_qe_init();
218#endif
219	/* invert AQR105 IRQ pins polarity */
220	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
221
222	return 0;
223}
224
225int config_board_mux(void)
226{
227	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
228	u32 usb_pwrfault;
229
230	if (hwconfig("qe-hdlc")) {
231		out_be32(&scfg->rcwpmuxcr0,
232			 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
233		printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
234		       in_be32(&scfg->rcwpmuxcr0));
235	} else {
236#ifdef CONFIG_HAS_FSL_XHCI_USB
237		out_be32(&scfg->rcwpmuxcr0, 0x3333);
238		out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
239		usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
240				SCFG_USBPWRFAULT_USB3_SHIFT) |
241				(SCFG_USBPWRFAULT_DEDICATED <<
242				SCFG_USBPWRFAULT_USB2_SHIFT) |
243				(SCFG_USBPWRFAULT_SHARED <<
244				 SCFG_USBPWRFAULT_USB1_SHIFT);
245		out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
246#endif
247	}
248	return 0;
249}
250
251#if defined(CONFIG_MISC_INIT_R)
252int misc_init_r(void)
253{
254	config_board_mux();
255	return 0;
256}
257#endif
258
259void fdt_del_qe(void *blob)
260{
261	int nodeoff = 0;
262
263	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
264				"fsl,qe")) >= 0) {
265		fdt_del_node(blob, nodeoff);
266	}
267}
268
269/* Update the address of the Aquantia PHY on the MDIO bus for boards revision
270 * v7.0 and up. Also rename the PHY node to align with the address change.
271 */
272void fdt_fixup_phy_addr(void *blob)
273{
274	const char phy_path[] =
275		"/soc/fman@1a00000/mdio@fd000/ethernet-phy@1";
276	int ret, offset, new_addr = AQR113C_PHY_ADDR;
277	char new_name[] = "ethernet-phy@00";
278
279	if (CPLD_READ(pcba_ver) < 0x7)
280		return;
281
282	offset = fdt_path_offset(blob, phy_path);
283	if (offset < 0) {
284		printf("ethernet-phy@1 node not found in the dts\n");
285		return;
286	}
287
288	ret = fdt_setprop_u32(blob, offset, "reg", new_addr);
289	if (ret < 0) {
290		printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
291		       fdt_strerror(ret));
292		return;
293	}
294
295	sprintf(new_name, "ethernet-phy@%x", new_addr);
296	ret = fdt_set_name(blob, offset, new_name);
297	if (ret < 0)
298		printf("Unable to rename node ethernet-phy@1: %s\n",
299		       fdt_strerror(ret));
300}
301
302int ft_board_setup(void *blob, struct bd_info *bd)
303{
304	u64 base[CONFIG_NR_DRAM_BANKS];
305	u64 size[CONFIG_NR_DRAM_BANKS];
306
307	/* fixup DT for the two DDR banks */
308	base[0] = gd->bd->bi_dram[0].start;
309	size[0] = gd->bd->bi_dram[0].size;
310	base[1] = gd->bd->bi_dram[1].start;
311	size[1] = gd->bd->bi_dram[1].size;
312
313	fdt_fixup_memory_banks(blob, base, size, 2);
314	ft_cpu_setup(blob, bd);
315
316#ifdef CONFIG_SYS_DPAA_FMAN
317#ifndef CONFIG_DM_ETH
318	fdt_fixup_fman_ethernet(blob);
319#endif
320	fdt_fixup_phy_addr(blob);
321#endif
322
323	fdt_fixup_icid(blob);
324
325	/*
326	 * qe-hdlc and usb multi-use the pins,
327	 * when set hwconfig to qe-hdlc, delete usb node.
328	 */
329	if (hwconfig("qe-hdlc"))
330#ifdef CONFIG_HAS_FSL_XHCI_USB
331		fdt_del_node_and_alias(blob, "usb1");
332#endif
333	/*
334	 * qe just support qe-uart and qe-hdlc,
335	 * if qe-uart and qe-hdlc are not set in hwconfig,
336	 * delete qe node.
337	 */
338	if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
339		fdt_del_qe(blob);
340
341	return 0;
342}
343
344void nand_fixup(void)
345{
346	u32 csor = 0;
347
348	if (CPLD_READ(pcba_ver) < 0x7)
349		return;
350
351    /* Change NAND Flash PGS/SPRZ configuration */
352	csor = CFG_SYS_NAND_CSOR;
353	if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
354		csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
355
356	if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64)
357		csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224;
358
359	if (IS_ENABLED(CONFIG_TFABOOT)) {
360		u8 cfg_rcw_src1, cfg_rcw_src2;
361		u16 cfg_rcw_src;
362
363		cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
364		cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
365		cpld_rev_bit(&cfg_rcw_src1);
366		cfg_rcw_src = cfg_rcw_src1;
367		cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
368
369		if (cfg_rcw_src == 0x25)
370			set_ifc_csor(IFC_CS1, csor);
371		else if (cfg_rcw_src == 0x118)
372			set_ifc_csor(IFC_CS0, csor);
373		else
374			printf("Invalid setting\n");
375	} else {
376		if (IS_ENABLED(CONFIG_NAND_BOOT))
377			set_ifc_csor(IFC_CS0, csor);
378		else
379			set_ifc_csor(IFC_CS1, csor);
380	}
381}
382
383#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
384int board_fix_fdt(void *blob)
385{
386	/* nand driver fix up */
387	nand_fixup();
388
389	/* fdt fix up */
390	fdt_fixup_phy_addr(blob);
391
392	return 0;
393}
394#endif
395
396u8 flash_read8(void *addr)
397{
398	return __raw_readb(addr + 1);
399}
400
401void flash_write16(u16 val, void *addr)
402{
403	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
404
405	__raw_writew(shftval, addr);
406}
407
408u16 flash_read16(void *addr)
409{
410	u16 val = __raw_readw(addr);
411
412	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
413}
414
415#endif
416