1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 * Copyright 2019-2020 NXP 5 */ 6 7#include <common.h> 8#include <clock_legacy.h> 9#include <i2c.h> 10#include <fdt_support.h> 11#include <fsl_ddr_sdram.h> 12#include <init.h> 13#include <log.h> 14#include <asm/global_data.h> 15#include <asm/io.h> 16#include <asm/arch/clock.h> 17#include <asm/arch/fsl_serdes.h> 18#include <asm/arch/fdt.h> 19#include <asm/arch/mmu.h> 20#include <asm/arch/cpu.h> 21#include <asm/arch/soc.h> 22#include <asm/arch-fsl-layerscape/fsl_icid.h> 23#include <ahci.h> 24#include <hwconfig.h> 25#include <mmc.h> 26#include <scsi.h> 27#include <fm_eth.h> 28#include <fsl_esdhc.h> 29#include <fsl_ifc.h> 30#include <spl.h> 31#include "../common/i2c_mux.h" 32 33#include "../common/qixis.h" 34#include "ls1043aqds_qixis.h" 35 36DECLARE_GLOBAL_DATA_PTR; 37 38enum { 39 MUX_TYPE_GPIO, 40}; 41 42/* LS1043AQDS serdes mux */ 43#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ 44#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ 45#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ 46#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ 47#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ 48#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ 49#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ 50#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ 51#define CFG_UART_MUX_MASK 0x6 52#define CFG_UART_MUX_SHIFT 1 53#define CFG_LPUART_EN 0x1 54 55#ifdef CONFIG_TFABOOT 56struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { 57 { 58 "nor0", 59 CFG_SYS_NOR0_CSPR, 60 CFG_SYS_NOR0_CSPR_EXT, 61 CFG_SYS_NOR_AMASK, 62 CFG_SYS_NOR_CSOR, 63 { 64 CFG_SYS_NOR_FTIM0, 65 CFG_SYS_NOR_FTIM1, 66 CFG_SYS_NOR_FTIM2, 67 CFG_SYS_NOR_FTIM3 68 }, 69 70 }, 71 { 72 "nor1", 73 CFG_SYS_NOR1_CSPR, 74 CFG_SYS_NOR1_CSPR_EXT, 75 CFG_SYS_NOR_AMASK, 76 CFG_SYS_NOR_CSOR, 77 { 78 CFG_SYS_NOR_FTIM0, 79 CFG_SYS_NOR_FTIM1, 80 CFG_SYS_NOR_FTIM2, 81 CFG_SYS_NOR_FTIM3 82 }, 83 }, 84 { 85 "nand", 86 CFG_SYS_NAND_CSPR, 87 CFG_SYS_NAND_CSPR_EXT, 88 CFG_SYS_NAND_AMASK, 89 CFG_SYS_NAND_CSOR, 90 { 91 CFG_SYS_NAND_FTIM0, 92 CFG_SYS_NAND_FTIM1, 93 CFG_SYS_NAND_FTIM2, 94 CFG_SYS_NAND_FTIM3 95 }, 96 }, 97 { 98 "fpga", 99 CFG_SYS_FPGA_CSPR, 100 CFG_SYS_FPGA_CSPR_EXT, 101 CFG_SYS_FPGA_AMASK, 102 CFG_SYS_FPGA_CSOR, 103 { 104 CFG_SYS_FPGA_FTIM0, 105 CFG_SYS_FPGA_FTIM1, 106 CFG_SYS_FPGA_FTIM2, 107 CFG_SYS_FPGA_FTIM3 108 }, 109 } 110}; 111 112struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { 113 { 114 "nand", 115 CFG_SYS_NAND_CSPR, 116 CFG_SYS_NAND_CSPR_EXT, 117 CFG_SYS_NAND_AMASK, 118 CFG_SYS_NAND_CSOR, 119 { 120 CFG_SYS_NAND_FTIM0, 121 CFG_SYS_NAND_FTIM1, 122 CFG_SYS_NAND_FTIM2, 123 CFG_SYS_NAND_FTIM3 124 }, 125 }, 126 { 127 "nor0", 128 CFG_SYS_NOR0_CSPR, 129 CFG_SYS_NOR0_CSPR_EXT, 130 CFG_SYS_NOR_AMASK, 131 CFG_SYS_NOR_CSOR, 132 { 133 CFG_SYS_NOR_FTIM0, 134 CFG_SYS_NOR_FTIM1, 135 CFG_SYS_NOR_FTIM2, 136 CFG_SYS_NOR_FTIM3 137 }, 138 }, 139 { 140 "nor1", 141 CFG_SYS_NOR1_CSPR, 142 CFG_SYS_NOR1_CSPR_EXT, 143 CFG_SYS_NOR_AMASK, 144 CFG_SYS_NOR_CSOR, 145 { 146 CFG_SYS_NOR_FTIM0, 147 CFG_SYS_NOR_FTIM1, 148 CFG_SYS_NOR_FTIM2, 149 CFG_SYS_NOR_FTIM3 150 }, 151 }, 152 { 153 "fpga", 154 CFG_SYS_FPGA_CSPR, 155 CFG_SYS_FPGA_CSPR_EXT, 156 CFG_SYS_FPGA_AMASK, 157 CFG_SYS_FPGA_CSOR, 158 { 159 CFG_SYS_FPGA_FTIM0, 160 CFG_SYS_FPGA_FTIM1, 161 CFG_SYS_FPGA_FTIM2, 162 CFG_SYS_FPGA_FTIM3 163 }, 164 } 165}; 166 167void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) 168{ 169 enum boot_src src = get_boot_src(); 170 171 if (src == BOOT_SOURCE_IFC_NAND) 172 regs_info->regs = ifc_cfg_nand_boot; 173 else 174 regs_info->regs = ifc_cfg_nor_boot; 175 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; 176} 177#endif 178 179int checkboard(void) 180{ 181#ifdef CONFIG_TFABOOT 182 enum boot_src src = get_boot_src(); 183#endif 184 char buf[64]; 185#ifndef CONFIG_SD_BOOT 186 u8 sw; 187#endif 188 189 puts("Board: LS1043AQDS, boot from "); 190 191#ifdef CONFIG_TFABOOT 192 if (src == BOOT_SOURCE_SD_MMC) 193 puts("SD\n"); 194 else { 195#endif 196 197#ifdef CONFIG_SD_BOOT 198 puts("SD\n"); 199#else 200 sw = QIXIS_READ(brdcfg[0]); 201 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 202 203 if (sw < 0x8) 204 printf("vBank: %d\n", sw); 205 else if (sw == 0x8) 206 puts("PromJet\n"); 207 else if (sw == 0x9) 208 puts("NAND\n"); 209 else if (sw == 0xF) 210 printf("QSPI\n"); 211 else 212 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 213#endif 214 215#ifdef CONFIG_TFABOOT 216 } 217#endif 218 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", 219 QIXIS_READ(id), QIXIS_READ(arch)); 220 221 printf("FPGA: v%d (%s), build %d\n", 222 (int)QIXIS_READ(scver), qixis_read_tag(buf), 223 (int)qixis_read_minor()); 224 225 return 0; 226} 227 228bool if_board_diff_clk(void) 229{ 230 u8 diff_conf = QIXIS_READ(brdcfg[11]); 231 232 return diff_conf & 0x40; 233} 234 235unsigned long get_board_sys_clk(void) 236{ 237 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 238 239 switch (sysclk_conf & 0x0f) { 240 case QIXIS_SYSCLK_64: 241 return 64000000; 242 case QIXIS_SYSCLK_83: 243 return 83333333; 244 case QIXIS_SYSCLK_100: 245 return 100000000; 246 case QIXIS_SYSCLK_125: 247 return 125000000; 248 case QIXIS_SYSCLK_133: 249 return 133333333; 250 case QIXIS_SYSCLK_150: 251 return 150000000; 252 case QIXIS_SYSCLK_160: 253 return 160000000; 254 case QIXIS_SYSCLK_166: 255 return 166666666; 256 } 257 258 return 66666666; 259} 260 261unsigned long get_board_ddr_clk(void) 262{ 263 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 264 265 if (if_board_diff_clk()) 266 return get_board_sys_clk(); 267 switch ((ddrclk_conf & 0x30) >> 4) { 268 case QIXIS_DDRCLK_100: 269 return 100000000; 270 case QIXIS_DDRCLK_125: 271 return 125000000; 272 case QIXIS_DDRCLK_133: 273 return 133333333; 274 } 275 276 return 66666666; 277} 278 279int dram_init(void) 280{ 281 /* 282 * When resuming from deep sleep, the I2C channel may not be 283 * in the default channel. So, switch to the default channel 284 * before accessing DDR SPD. 285 * 286 * PCA9547 mount on I2C1 bus 287 */ 288 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); 289 fsl_initdram(); 290#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ 291 defined(CONFIG_SPL_BUILD) 292 /* This will break-before-make MMU for DDR */ 293 update_early_mmu_table(); 294#endif 295 296 return 0; 297} 298 299int i2c_multiplexer_select_vid_channel(u8 channel) 300{ 301 return select_i2c_ch_pca9547(channel, 0); 302} 303 304void board_retimer_init(void) 305{ 306 u8 reg; 307 int bus_num = 0; 308 309 /* Retimer is connected to I2C1_CH7_CH5 */ 310 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); 311 reg = I2C_MUX_CH5; 312#if CONFIG_IS_ENABLED(DM_I2C) 313 struct udevice *dev; 314 int ret; 315 316 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, 317 1, &dev); 318 if (ret) { 319 printf("%s: Cannot find udev for a bus %d\n", __func__, 320 bus_num); 321 return; 322 } 323 dm_i2c_write(dev, 0, ®, 1); 324 325 /* Access to Control/Shared register */ 326 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, 327 1, &dev); 328 if (ret) { 329 printf("%s: Cannot find udev for a bus %d\n", __func__, 330 bus_num); 331 return; 332 } 333 334 reg = 0x0; 335 dm_i2c_write(dev, 0xff, ®, 1); 336 337 /* Read device revision and ID */ 338 dm_i2c_read(dev, 1, ®, 1); 339 debug("Retimer version id = 0x%x\n", reg); 340 341 /* Enable Broadcast. All writes target all channel register sets */ 342 reg = 0x0c; 343 dm_i2c_write(dev, 0xff, ®, 1); 344 345 /* Reset Channel Registers */ 346 dm_i2c_read(dev, 0, ®, 1); 347 reg |= 0x4; 348 dm_i2c_write(dev, 0, ®, 1); 349 350 /* Enable override divider select and Enable Override Output Mux */ 351 dm_i2c_read(dev, 9, ®, 1); 352 reg |= 0x24; 353 dm_i2c_write(dev, 9, ®, 1); 354 355 /* Select VCO Divider to full rate (000) */ 356 dm_i2c_read(dev, 0x18, ®, 1); 357 reg &= 0x8f; 358 dm_i2c_write(dev, 0x18, ®, 1); 359 360 /* Selects active PFD MUX Input as Re-timed Data (001) */ 361 dm_i2c_read(dev, 0x1e, ®, 1); 362 reg &= 0x3f; 363 reg |= 0x20; 364 dm_i2c_write(dev, 0x1e, ®, 1); 365 366 /* Set data rate as 10.3125 Gbps */ 367 reg = 0x0; 368 dm_i2c_write(dev, 0x60, ®, 1); 369 reg = 0xb2; 370 dm_i2c_write(dev, 0x61, ®, 1); 371 reg = 0x90; 372 dm_i2c_write(dev, 0x62, ®, 1); 373 reg = 0xb3; 374 dm_i2c_write(dev, 0x63, ®, 1); 375 reg = 0xcd; 376 dm_i2c_write(dev, 0x64, ®, 1); 377#else 378 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); 379 380 /* Access to Control/Shared register */ 381 reg = 0x0; 382 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 383 384 /* Read device revision and ID */ 385 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 386 debug("Retimer version id = 0x%x\n", reg); 387 388 /* Enable Broadcast. All writes target all channel register sets */ 389 reg = 0x0c; 390 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 391 392 /* Reset Channel Registers */ 393 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 394 reg |= 0x4; 395 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 396 397 /* Enable override divider select and Enable Override Output Mux */ 398 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); 399 reg |= 0x24; 400 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); 401 402 /* Select VCO Divider to full rate (000) */ 403 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 404 reg &= 0x8f; 405 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 406 407 /* Selects active PFD MUX Input as Re-timed Data (001) */ 408 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 409 reg &= 0x3f; 410 reg |= 0x20; 411 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 412 413 /* Set data rate as 10.3125 Gbps */ 414 reg = 0x0; 415 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 416 reg = 0xb2; 417 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 418 reg = 0x90; 419 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 420 reg = 0xb3; 421 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 422 reg = 0xcd; 423 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 424#endif 425 426 /* Return the default channel */ 427 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); 428} 429 430int board_early_init_f(void) 431{ 432 u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; 433#ifdef CONFIG_HAS_FSL_XHCI_USB 434 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; 435 u32 usb_pwrfault; 436#endif 437#ifdef CONFIG_LPUART 438 u8 uart; 439#endif 440 441 /* 442 * Enable secure system counter for timer 443 */ 444 out_le32(cntcr, 0x1); 445 446#if defined(CONFIG_SYS_I2C_EARLY_INIT) 447 i2c_early_init_f(); 448#endif 449 fsl_lsch2_early_init_f(); 450 451#ifdef CONFIG_HAS_FSL_XHCI_USB 452 out_be32(&scfg->rcwpmuxcr0, 0x3333); 453 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 454 usb_pwrfault = 455 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | 456 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | 457 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); 458 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 459#endif 460 461#ifdef CONFIG_LPUART 462 /* We use lpuart0 as system console */ 463 uart = QIXIS_READ(brdcfg[14]); 464 uart &= ~CFG_UART_MUX_MASK; 465 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; 466 QIXIS_WRITE(brdcfg[14], uart); 467#endif 468 469 return 0; 470} 471 472#ifdef CONFIG_FSL_DEEP_SLEEP 473/* determine if it is a warm boot */ 474bool is_warm_boot(void) 475{ 476#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) 477 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; 478 479 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) 480 return 1; 481 482 return 0; 483} 484#endif 485 486int config_board_mux(int ctrl_type) 487{ 488 u8 reg14; 489 490 reg14 = QIXIS_READ(brdcfg[14]); 491 492 switch (ctrl_type) { 493 case MUX_TYPE_GPIO: 494 reg14 = (reg14 & (~0x30)) | 0x20; 495 break; 496 default: 497 puts("Unsupported mux interface type\n"); 498 return -1; 499 } 500 501 QIXIS_WRITE(brdcfg[14], reg14); 502 503 return 0; 504} 505 506int config_serdes_mux(void) 507{ 508 return 0; 509} 510 511 512#ifdef CONFIG_MISC_INIT_R 513int misc_init_r(void) 514{ 515 if (hwconfig("gpio")) 516 config_board_mux(MUX_TYPE_GPIO); 517 518 return 0; 519} 520#endif 521 522int board_init(void) 523{ 524#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 525 erratum_a010315(); 526#endif 527 528 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); 529 board_retimer_init(); 530 531#ifdef CFG_SYS_FSL_SERDES 532 config_serdes_mux(); 533#endif 534 535 return 0; 536} 537 538#ifdef CONFIG_OF_BOARD_SETUP 539int ft_board_setup(void *blob, struct bd_info *bd) 540{ 541 u64 base[CONFIG_NR_DRAM_BANKS]; 542 u64 size[CONFIG_NR_DRAM_BANKS]; 543 u8 reg; 544 545 /* fixup DT for the two DDR banks */ 546 base[0] = gd->bd->bi_dram[0].start; 547 size[0] = gd->bd->bi_dram[0].size; 548 base[1] = gd->bd->bi_dram[1].start; 549 size[1] = gd->bd->bi_dram[1].size; 550 551 fdt_fixup_memory_banks(blob, base, size, 2); 552 ft_cpu_setup(blob, bd); 553 554#ifdef CONFIG_FMAN_ENET 555 fdt_fixup_board_enet(blob); 556#endif 557 558 fdt_fixup_icid(blob); 559 560 reg = QIXIS_READ(brdcfg[0]); 561 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 562 563 /* Disable IFC if QSPI is enabled */ 564 if (reg == 0xF) 565 do_fixup_by_compat(blob, "fsl,ifc", 566 "status", "disabled", 8 + 1, 1); 567 568 return 0; 569} 570#endif 571 572u8 flash_read8(void *addr) 573{ 574 return __raw_readb(addr + 1); 575} 576 577void flash_write16(u16 val, void *addr) 578{ 579 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 580 581 __raw_writew(shftval, addr); 582} 583 584u16 flash_read16(void *addr) 585{ 586 u16 val = __raw_readw(addr); 587 588 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 589} 590 591#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) 592void *env_sf_get_env_addr(void) 593{ 594 return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); 595} 596#endif 597