1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6#include <common.h>
7#include <fsl_ddr_sdram.h>
8#include <fsl_ddr_dimm_params.h>
9#ifdef CONFIG_FSL_DEEP_SLEEP
10#include <fsl_sleep.h>
11#endif
12#include <log.h>
13#include <asm/arch/clock.h>
14#include <asm/global_data.h>
15#include "ddr.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19void fsl_ddr_board_options(memctl_options_t *popts,
20			   dimm_params_t *pdimm,
21			   unsigned int ctrl_num)
22{
23	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
24	ulong ddr_freq;
25
26	if (ctrl_num > 3) {
27		printf("Not supported controller number %d\n", ctrl_num);
28		return;
29	}
30	if (!pdimm->n_ranks)
31		return;
32
33	pbsp = udimms[0];
34
35	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
36	 * freqency and n_banks specified in board_specific_parameters table.
37	 */
38	ddr_freq = get_ddr_freq(0) / 1000000;
39	while (pbsp->datarate_mhz_high) {
40		if (pbsp->n_ranks == pdimm->n_ranks) {
41			if (ddr_freq <= pbsp->datarate_mhz_high) {
42				popts->clk_adjust = pbsp->clk_adjust;
43				popts->wrlvl_start = pbsp->wrlvl_start;
44				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
45				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
46				popts->cpo_override = pbsp->cpo_override;
47				popts->write_data_delay =
48					pbsp->write_data_delay;
49				goto found;
50			}
51			pbsp_highest = pbsp;
52		}
53		pbsp++;
54	}
55
56	if (pbsp_highest) {
57		printf("Error: board specific timing not found for %lu MT/s\n",
58		       ddr_freq);
59		printf("Trying to use the highest speed (%u) parameters\n",
60		       pbsp_highest->datarate_mhz_high);
61		popts->clk_adjust = pbsp_highest->clk_adjust;
62		popts->wrlvl_start = pbsp_highest->wrlvl_start;
63		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
64		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
65	} else {
66		panic("DIMM is not supported by this board");
67	}
68found:
69	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
70	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
71
72	/* force DDR bus width to 32 bits */
73	popts->data_bus_width = 1;
74	popts->otf_burst_chop_en = 0;
75	popts->burst_length = DDR_BL8;
76	popts->bstopre = 0;		/* enable auto precharge */
77
78	/*
79	 * Factors to consider for half-strength driver enable:
80	 *	- number of DIMMs installed
81	 */
82	popts->half_strength_driver_enable = 1;
83	/*
84	 * Write leveling override
85	 */
86	popts->wrlvl_override = 1;
87	popts->wrlvl_sample = 0xf;
88
89	/*
90	 * Rtt and Rtt_WR override
91	 */
92	popts->rtt_override = 0;
93
94	/* Enable ZQ calibration */
95	popts->zq_en = 1;
96
97#ifdef CONFIG_SYS_FSL_DDR4
98	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
99	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
100			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
101
102	/* optimize cpo for erratum A-009942 */
103	popts->cpo_sample = 0x59;
104#else
105	popts->cswl_override = DDR_CSWL_CS0;
106
107	/* DHC_EN =1, ODT = 75 Ohm */
108	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
109	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
110#endif
111}
112
113#ifdef CONFIG_TFABOOT
114int fsl_initdram(void)
115{
116	gd->ram_size = tfa_get_dram_size();
117	if (!gd->ram_size)
118		gd->ram_size = fsl_ddr_sdram_size();
119
120	return 0;
121}
122#else
123int fsl_initdram(void)
124{
125	phys_size_t dram_size;
126
127#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
128	gd->ram_size = fsl_ddr_sdram_size();
129
130	return 0;
131#else
132	puts("Initializing DDR....using SPD\n");
133
134	dram_size = fsl_ddr_sdram();
135#endif
136	erratum_a008850_post();
137
138#ifdef CONFIG_FSL_DEEP_SLEEP
139	fsl_dp_ddr_restore();
140#endif
141
142	gd->ram_size = dram_size;
143
144	return 0;
145}
146#endif
147