1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2021 NXP 5 */ 6 7#include <common.h> 8#include <i2c.h> 9#include <fdt_support.h> 10#include <asm/cache.h> 11#include <init.h> 12#include <asm/global_data.h> 13#include <asm/io.h> 14#include <asm/arch/clock.h> 15#include <asm/arch/fsl_serdes.h> 16#include <asm/arch/fdt.h> 17#include <asm/arch/mmu.h> 18#include <asm/arch/soc.h> 19#include <ahci.h> 20#include <hwconfig.h> 21#include <mmc.h> 22#include <env_internal.h> 23#include <scsi.h> 24#include <fm_eth.h> 25#include <fsl_esdhc.h> 26#include <fsl_mmdc.h> 27#include <spl.h> 28#include <netdev.h> 29#include "../common/qixis.h" 30#include "ls1012aqds_qixis.h" 31#include "ls1012aqds_pfe.h" 32#include <net/pfe_eth/pfe/pfe_hw.h> 33 34DECLARE_GLOBAL_DATA_PTR; 35 36int checkboard(void) 37{ 38 char buf[64]; 39 u8 sw; 40 41 sw = QIXIS_READ(arch); 42 printf("Board Arch: V%d, ", sw >> 4); 43 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 44 45 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); 46 47 if (sw & QIXIS_LBMAP_ALTBANK) 48 printf("flash: 2\n"); 49 else 50 printf("flash: 1\n"); 51 52 printf("FPGA: v%d (%s), build %d", 53 (int)QIXIS_READ(scver), qixis_read_tag(buf), 54 (int)qixis_read_minor()); 55 56 /* the timestamp string contains "\n" at the end */ 57 printf(" on %s", qixis_read_time(buf)); 58 return 0; 59} 60 61#ifdef CONFIG_TFABOOT 62int dram_init(void) 63{ 64 gd->ram_size = tfa_get_dram_size(); 65 if (!gd->ram_size) 66 gd->ram_size = CFG_SYS_SDRAM_SIZE; 67 68 return 0; 69} 70#else 71int dram_init(void) 72{ 73 static const struct fsl_mmdc_info mparam = { 74 0x05180000, /* mdctl */ 75 0x00030035, /* mdpdc */ 76 0x12554000, /* mdotc */ 77 0xbabf7954, /* mdcfg0 */ 78 0xdb328f64, /* mdcfg1 */ 79 0x01ff00db, /* mdcfg2 */ 80 0x00001680, /* mdmisc */ 81 0x0f3c8000, /* mdref */ 82 0x00002000, /* mdrwd */ 83 0x00bf1023, /* mdor */ 84 0x0000003f, /* mdasp */ 85 0x0000022a, /* mpodtctrl */ 86 0xa1390003, /* mpzqhwctrl */ 87 }; 88 89 mmdc_init(&mparam); 90 gd->ram_size = CFG_SYS_SDRAM_SIZE; 91#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 92 /* This will break-before-make MMU for DDR */ 93 update_early_mmu_table(); 94#endif 95 96 return 0; 97} 98#endif 99 100int board_early_init_f(void) 101{ 102 fsl_lsch2_early_init_f(); 103 104 return 0; 105} 106 107#ifdef CONFIG_MISC_INIT_R 108int misc_init_r(void) 109{ 110 u8 mux_sdhc_cd = 0x80; 111 int bus_num = 0; 112 113#if CONFIG_IS_ENABLED(DM_I2C) 114 struct udevice *dev; 115 int ret; 116 117 ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, 118 1, &dev); 119 if (ret) { 120 printf("%s: Cannot find udev for a bus %d\n", __func__, 121 bus_num); 122 return ret; 123 } 124 dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); 125#else 126 i2c_set_bus_num(bus_num); 127 128 i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); 129#endif 130 131 return 0; 132} 133#endif 134 135int board_init(void) 136{ 137 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 138 CONFIG_SYS_CCI400_OFFSET); 139 140 /* Set CCI-400 control override register to enable barrier 141 * transaction */ 142 if (current_el() == 3) 143 out_le32(&cci->ctrl_ord, 144 CCI400_CTRLORD_EN_BARRIER); 145 146#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 147 erratum_a010315(); 148#endif 149 150 return 0; 151} 152 153#ifdef CONFIG_FSL_PFE 154void board_quiesce_devices(void) 155{ 156 pfe_command_stop(0, NULL); 157} 158#endif 159 160int esdhc_status_fixup(void *blob, const char *compat) 161{ 162 char esdhc0_path[] = "/soc/esdhc@1560000"; 163 char esdhc1_path[] = "/soc/esdhc@1580000"; 164 u8 card_id; 165 166 do_fixup_by_path(blob, esdhc0_path, "status", "okay", 167 sizeof("okay"), 1); 168 169 /* 170 * The Presence Detect 2 register detects the installation 171 * of cards in various PCI Express or SGMII slots. 172 * 173 * STAT_PRS2[7:5]: Specifies the type of card installed in the 174 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. 175 */ 176 card_id = (QIXIS_READ(present2) & 0xe0) >> 5; 177 178 /* If no adapter is installed in SDHC2, disable SDHC2 */ 179 if (card_id == 0x7) 180 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 181 sizeof("disabled"), 1); 182 else 183 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 184 sizeof("okay"), 1); 185 return 0; 186} 187 188static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val, 189 char *enet_path, char *mdio_path) 190{ 191 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id", 192 &prop_val.busid, PFE_PROP_LEN, 1); 193 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id", 194 &prop_val.phyid, PFE_PROP_LEN, 1); 195 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val", 196 &prop_val.mux_val, PFE_PROP_LEN, 1); 197 do_fixup_by_path(set_blob, enet_path, "phy-mode", 198 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1); 199 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask", 200 &prop_val.phy_mask, PFE_PROP_LEN, 1); 201 return 0; 202} 203 204static void fdt_fsl_fixup_of_pfe(void *blob) 205{ 206 int i = 0; 207 struct pfe_prop_val prop_val; 208 void *l_blob = blob; 209 210 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; 211 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & 212 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; 213 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; 214 215 for (i = 0; i < NUM_ETH_NODE; i++) { 216 switch (srds_s1) { 217 case SERDES_1_G_PROTOCOL: 218 if (i == 0) { 219 prop_val.busid = cpu_to_fdt32( 220 ETH_1_1G_BUS_ID); 221 prop_val.phyid = cpu_to_fdt32( 222 ETH_1_1G_PHY_ID); 223 prop_val.mux_val = cpu_to_fdt32( 224 ETH_1_1G_MDIO_MUX); 225 prop_val.phy_mask = cpu_to_fdt32( 226 ETH_1G_MDIO_PHY_MASK); 227 prop_val.phy_mode = "sgmii"; 228 pfe_set_properties(l_blob, prop_val, ETH_1_PATH, 229 ETH_1_MDIO); 230 } else { 231 prop_val.busid = cpu_to_fdt32( 232 ETH_2_1G_BUS_ID); 233 prop_val.phyid = cpu_to_fdt32( 234 ETH_2_1G_PHY_ID); 235 prop_val.mux_val = cpu_to_fdt32( 236 ETH_2_1G_MDIO_MUX); 237 prop_val.phy_mask = cpu_to_fdt32( 238 ETH_1G_MDIO_PHY_MASK); 239 prop_val.phy_mode = "rgmii"; 240 pfe_set_properties(l_blob, prop_val, ETH_2_PATH, 241 ETH_2_MDIO); 242 } 243 break; 244 case SERDES_2_5_G_PROTOCOL: 245 if (i == 0) { 246 prop_val.busid = cpu_to_fdt32( 247 ETH_1_2_5G_BUS_ID); 248 prop_val.phyid = cpu_to_fdt32( 249 ETH_1_2_5G_PHY_ID); 250 prop_val.mux_val = cpu_to_fdt32( 251 ETH_1_2_5G_MDIO_MUX); 252 prop_val.phy_mask = cpu_to_fdt32( 253 ETH_2_5G_MDIO_PHY_MASK); 254 prop_val.phy_mode = "2500base-x"; 255 pfe_set_properties(l_blob, prop_val, ETH_1_PATH, 256 ETH_1_MDIO); 257 } else { 258 prop_val.busid = cpu_to_fdt32( 259 ETH_2_2_5G_BUS_ID); 260 prop_val.phyid = cpu_to_fdt32( 261 ETH_2_2_5G_PHY_ID); 262 prop_val.mux_val = cpu_to_fdt32( 263 ETH_2_2_5G_MDIO_MUX); 264 prop_val.phy_mask = cpu_to_fdt32( 265 ETH_2_5G_MDIO_PHY_MASK); 266 prop_val.phy_mode = "2500base-x"; 267 pfe_set_properties(l_blob, prop_val, ETH_2_PATH, 268 ETH_2_MDIO); 269 } 270 break; 271 default: 272 printf("serdes:[%d]\n", srds_s1); 273 } 274 } 275} 276 277#ifdef CONFIG_OF_BOARD_SETUP 278int ft_board_setup(void *blob, struct bd_info *bd) 279{ 280 arch_fixup_fdt(blob); 281 282 ft_cpu_setup(blob, bd); 283 fdt_fsl_fixup_of_pfe(blob); 284 285 return 0; 286} 287#endif 288