1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019, 2021 NXP
4 */
5
6#include <common.h>
7#include <command.h>
8#include <cpu_func.h>
9#include <hang.h>
10#include <image.h>
11#include <init.h>
12#include <log.h>
13#include <spl.h>
14#include <asm/global_data.h>
15#include <asm/io.h>
16#include <asm/mach-imx/iomux-v3.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/imx8mm_pins.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/mach-imx/boot_mode.h>
21#include <asm/arch/ddr.h>
22#include <asm/sections.h>
23
24#include <dm/uclass.h>
25#include <dm/device.h>
26#include <dm/uclass-internal.h>
27#include <dm/device-internal.h>
28
29#include <power/pmic.h>
30#include <power/pca9450.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34int spl_board_boot_device(enum boot_device boot_dev_spl)
35{
36	switch (boot_dev_spl) {
37	case USB_BOOT:
38		return BOOT_DEVICE_BOARD;
39	case SD2_BOOT:
40	case MMC2_BOOT:
41		return BOOT_DEVICE_MMC1;
42	case SD3_BOOT:
43	case MMC3_BOOT:
44		return BOOT_DEVICE_MMC2;
45	case QSPI_BOOT:
46		return BOOT_DEVICE_NOR;
47	default:
48		return BOOT_DEVICE_NONE;
49	}
50}
51
52static void spl_dram_init(void)
53{
54	ddr_init(&dram_timing);
55}
56
57void spl_board_init(void)
58{
59	arch_misc_init();
60}
61
62#ifdef CONFIG_SPL_LOAD_FIT
63int board_fit_config_name_match(const char *name)
64{
65	/* Just empty function now - can't decide what to choose */
66	debug("%s: %s\n", __func__, name);
67
68	return 0;
69}
70#endif
71
72static int power_init_board(void)
73{
74	struct udevice *dev;
75	int ret;
76
77	ret = pmic_get("pca9450@25", &dev);
78	if (ret == -ENODEV) {
79		puts("No pmic\n");
80		return 0;
81	}
82	if (ret != 0)
83		return ret;
84
85	/* BUCKxOUT_DVS0/1 control BUCK123 output */
86	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
87
88	/* Buck 1 DVS control through PMIC_STBY_REQ */
89	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
90
91	/* Set DVS1 to 0.8v for suspend */
92	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
93
94	/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
95	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
96
97	/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
98	pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
99
100	/* set VDD_SNVS_0V8 from default 0.85V */
101	pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
102
103	return 0;
104}
105
106void board_init_f(ulong dummy)
107{
108	struct udevice *dev;
109	int ret;
110
111	arch_cpu_init();
112
113	init_uart_clk(1);
114
115	timer_init();
116
117	/* Clear the BSS. */
118	memset(__bss_start, 0, __bss_end - __bss_start);
119
120	ret = spl_early_init();
121	if (ret) {
122		debug("spl_early_init() failed: %d\n", ret);
123		hang();
124	}
125
126	ret = uclass_get_device_by_name(UCLASS_CLK,
127					"clock-controller@30380000",
128					&dev);
129	if (ret < 0) {
130		printf("Failed to find clock node. Check device tree\n");
131		hang();
132	}
133
134	preloader_console_init();
135
136	enable_tzc380();
137
138	power_init_board();
139
140	/* DDR initialization */
141	spl_dram_init();
142
143	board_init_r(NULL, 0);
144}
145