1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on da830evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 */
10
11#include <common.h>
12#include <dm.h>
13#include <env.h>
14#include <i2c.h>
15#include <init.h>
16#include <net.h>
17#include <spi.h>
18#include <spi_flash.h>
19#include <asm/arch/hardware.h>
20#include <asm/global_data.h>
21#include <asm/ti-common/davinci_nand.h>
22#include <asm/arch/emac_defs.h>
23#include <asm/arch/pinmux_defs.h>
24#include <asm/io.h>
25#include <asm/arch/davinci_misc.h>
26#include <linux/errno.h>
27#include <hwconfig.h>
28#include <asm/mach-types.h>
29#include <asm/gpio.h>
30
31#ifdef CONFIG_MMC_DAVINCI
32#include <mmc.h>
33#include <asm/arch/sdmmc_defs.h>
34#endif
35
36DECLARE_GLOBAL_DATA_PTR;
37
38#ifdef CONFIG_DRIVER_TI_EMAC
39#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
40#define HAS_RMII 1
41#else
42#define HAS_RMII 0
43#endif
44#endif /* CONFIG_DRIVER_TI_EMAC */
45
46#define CFG_MAC_ADDR_SPI_BUS	0
47#define CFG_MAC_ADDR_SPI_CS	0
48#define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
49#define CFG_MAC_ADDR_SPI_MODE	SPI_MODE_3
50
51#define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)
52
53#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
54static int get_mac_addr(u8 *addr)
55{
56	struct spi_flash *flash;
57	int ret;
58
59	flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
60			CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
61	if (!flash) {
62		printf("Error - unable to probe SPI flash.\n");
63		return -1;
64	}
65
66	ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
67	if (ret) {
68		printf("Error - unable to read MAC address from SPI flash.\n");
69		return -1;
70	}
71
72	return ret;
73}
74#endif
75
76void dsp_lpsc_on(unsigned domain, unsigned int id)
77{
78	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
79	struct davinci_psc_regs *psc_regs;
80
81	psc_regs = davinci_psc0_regs;
82	mdstat = &psc_regs->psc0.mdstat[id];
83	mdctl = &psc_regs->psc0.mdctl[id];
84	ptstat = &psc_regs->ptstat;
85	ptcmd = &psc_regs->ptcmd;
86
87	while (*ptstat & (0x1 << domain))
88		;
89
90	if ((*mdstat & 0x1f) == 0x03)
91		return;                 /* Already on and enabled */
92
93	*mdctl |= 0x03;
94
95	*ptcmd = 0x1 << domain;
96
97	while (*ptstat & (0x1 << domain))
98		;
99	while ((*mdstat & 0x1f) != 0x03)
100		;		/* Probably an overkill... */
101}
102
103static void dspwake(void)
104{
105	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
106	u32 val;
107
108	/* if the device is ARM only, return */
109	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
110		return;
111
112	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
113		return;
114
115	*resetvect++ = 0x1E000; /* DSP Idle */
116	/* clear out the next 10 words as NOP */
117	memset(resetvect, 0, sizeof(unsigned) *10);
118
119	/* setup the DSP reset vector */
120	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
121
122	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
123	val = readl(PSC0_MDCTL + (15 * 4));
124	val |= 0x100;
125	writel(val, (PSC0_MDCTL + (15 * 4)));
126}
127
128int misc_init_r(void)
129{
130	dspwake();
131
132#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH)
133	uchar env_enetaddr[6], buff[6];
134	int enetaddr_found, spi_mac_read;
135
136	enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
137
138	spi_mac_read = get_mac_addr(buff);
139	buff[0] = 0;
140
141	/*
142	 * MAC address not present in the environment
143	 * try and read the MAC address from SPI flash
144	 * and set it.
145	 */
146	if (!enetaddr_found) {
147		if (!spi_mac_read) {
148			if (is_valid_ethaddr(buff)) {
149				if (eth_env_set_enetaddr("ethaddr", buff)) {
150					printf("Warning: Failed to "
151					"set MAC address from SPI flash\n");
152				}
153			} else {
154					printf("Warning: Invalid "
155					"MAC address read from SPI flash\n");
156			}
157		}
158	} else {
159		/*
160		 * MAC address present in environment compare it with
161		 * the MAC address in SPI flash and warn on mismatch
162		 */
163		if (!spi_mac_read && is_valid_ethaddr(buff) &&
164		    memcmp(env_enetaddr, buff, 6))
165			printf("Warning: MAC address in SPI flash don't match "
166					"with the MAC address in the environment\n");
167		printf("Default using MAC address from environment\n");
168	}
169#endif
170	return 0;
171}
172
173static const struct pinmux_config gpio_pins[] = {
174#ifdef CONFIG_MTD_NOR_FLASH
175	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
176	{ pinmux(0), 8, 4 },	/* GP0[11] */
177#endif
178#ifdef CONFIG_MMC_DAVINCI
179	/* GP0[11] is required for SD to work on Rev 3 EVMs */
180	{ pinmux(0),  8, 4 },	/* GP0[11] */
181#endif
182};
183
184const struct pinmux_resource pinmuxes[] = {
185#ifdef CONFIG_DRIVER_TI_EMAC
186	PINMUX_ITEM(emac_pins_mdio),
187#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
188	PINMUX_ITEM(emac_pins_rmii),
189#else
190	PINMUX_ITEM(emac_pins_mii),
191#endif
192#endif
193#ifdef CONFIG_SPI_FLASH
194	PINMUX_ITEM(spi1_pins_base),
195	PINMUX_ITEM(spi1_pins_scs0),
196#endif
197	PINMUX_ITEM(uart2_pins_txrx),
198	PINMUX_ITEM(uart2_pins_rtscts),
199	PINMUX_ITEM(i2c0_pins),
200#ifdef CONFIG_NAND_DAVINCI
201	PINMUX_ITEM(emifa_pins_cs3),
202	PINMUX_ITEM(emifa_pins_cs4),
203	PINMUX_ITEM(emifa_pins_nand),
204#elif defined(CONFIG_MTD_NOR_FLASH)
205	PINMUX_ITEM(emifa_pins_cs2),
206	PINMUX_ITEM(emifa_pins_nor),
207#endif
208	PINMUX_ITEM(gpio_pins),
209#ifdef CONFIG_MMC_DAVINCI
210	PINMUX_ITEM(mmc0_pins),
211#endif
212};
213
214const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
215
216const struct lpsc_resource lpsc[] = {
217	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
218	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
219	{ DAVINCI_LPSC_EMAC },	/* image download */
220	{ DAVINCI_LPSC_UART2 },	/* console */
221	{ DAVINCI_LPSC_GPIO },
222#ifdef CONFIG_MMC_DAVINCI
223	{ DAVINCI_LPSC_MMC_SD },
224#endif
225};
226
227const int lpsc_size = ARRAY_SIZE(lpsc);
228
229#ifndef CFG_DA850_EVM_MAX_CPU_CLK
230#define CFG_DA850_EVM_MAX_CPU_CLK	300000000
231#endif
232
233#define REV_AM18X_EVM		0x100
234
235#ifdef CONFIG_REVISION_TAG
236/*
237 * get_board_rev() - setup to pass kernel board revision information
238 * Returns:
239 * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
240 *		0000b - 300 MHz
241 *		0001b - 372 MHz
242 *		0010b - 408 MHz
243 *		0011b - 456 MHz
244 */
245u32 get_board_rev(void)
246{
247	char *s;
248	u32 maxcpuclk = CFG_DA850_EVM_MAX_CPU_CLK;
249	u32 rev = 0;
250
251	s = env_get("maxcpuclk");
252	if (s)
253		maxcpuclk = dectoul(s, NULL);
254
255	if (maxcpuclk >= 456000000)
256		rev = 3;
257	else if (maxcpuclk >= 408000000)
258		rev = 2;
259	else if (maxcpuclk >= 372000000)
260		rev = 1;
261	return rev;
262}
263#endif
264
265int board_early_init_f(void)
266{
267	/*
268	 * Power on required peripherals
269	 * ARM does not have access by default to PSC0 and PSC1
270	 * assuming here that the DSP bootloader has set the IOPU
271	 * such that PSC access is available to ARM
272	 */
273	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
274		return 1;
275
276	return 0;
277}
278
279int board_init(void)
280{
281	irq_init();
282
283#ifdef CONFIG_NAND_DAVINCI
284	/*
285	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
286	 * Linux kernel @ 25MHz EMIFA
287	 */
288	writel((DAVINCI_ABCR_WSETUP(2) |
289		DAVINCI_ABCR_WSTROBE(2) |
290		DAVINCI_ABCR_WHOLD(1) |
291		DAVINCI_ABCR_RSETUP(1) |
292		DAVINCI_ABCR_RSTROBE(4) |
293		DAVINCI_ABCR_RHOLD(0) |
294		DAVINCI_ABCR_TA(1) |
295		DAVINCI_ABCR_ASIZE_8BIT),
296	       &davinci_emif_regs->ab2cr); /* CS3 */
297#endif
298
299	/* arch number of the board */
300	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
301
302	/* address of boot parameters */
303	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
304
305	/* setup the SUSPSRC for ARM to control emulation suspend */
306	writel(readl(&davinci_syscfg_regs->suspsrc) &
307	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
308		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
309		 DAVINCI_SYSCFG_SUSPSRC_UART2),
310	       &davinci_syscfg_regs->suspsrc);
311
312#ifdef CONFIG_MTD_NOR_FLASH
313	/* Set the GPIO direction as output */
314	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
315
316	/* Set the output as low */
317	writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
318#endif
319
320#ifdef CONFIG_MMC_DAVINCI
321	/* Set the GPIO direction as output */
322	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
323
324	/* Set the output as high */
325	writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
326#endif
327
328#ifdef CONFIG_DRIVER_TI_EMAC
329	davinci_emac_mii_mode_sel(HAS_RMII);
330#endif /* CONFIG_DRIVER_TI_EMAC */
331
332	return 0;
333}
334
335#ifdef CONFIG_DRIVER_TI_EMAC
336
337#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
338/**
339 * rmii_hw_init
340 *
341 * DA850/OMAP-L138 EVM can interface to a daughter card for
342 * additional features. This card has an I2C GPIO Expander TCA6416
343 * to select the required functions like camera, RMII Ethernet,
344 * character LCD, video.
345 *
346 * Initialization of the expander involves configuring the
347 * polarity and direction of the ports. P07-P05 are used here.
348 * These ports are connected to a Mux chip which enables only one
349 * functionality at a time.
350 *
351 * For RMII phy to respond, the MII MDIO clock has to be  disabled
352 * since both the PHY devices have address as zero. The MII MDIO
353 * clock is controlled via GPIO2[6].
354 *
355 * This code is valid for Beta version of the hardware
356 */
357int rmii_hw_init(void)
358{
359	const struct pinmux_config gpio_pins[] = {
360		{ pinmux(6), 8, 1 }
361	};
362	u_int8_t buf[2];
363	unsigned int temp;
364	int ret;
365
366	/* PinMux for GPIO */
367	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
368		return 1;
369
370	/* I2C Exapnder configuration */
371	/* Set polarity to non-inverted */
372	buf[0] = 0x0;
373	buf[1] = 0x0;
374	ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
375	if (ret) {
376		printf("\nExpander @ 0x%02x write FAILED!!!\n",
377				CFG_SYS_I2C_EXPANDER_ADDR);
378		return ret;
379	}
380
381	/* Configure P07-P05 as outputs */
382	buf[0] = 0x1f;
383	buf[1] = 0xff;
384	ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
385	if (ret) {
386		printf("\nExpander @ 0x%02x write FAILED!!!\n",
387				CFG_SYS_I2C_EXPANDER_ADDR);
388	}
389
390	/* For Ethernet RMII selection
391	 * P07(SelA)=0
392	 * P06(SelB)=1
393	 * P05(SelC)=1
394	 */
395	if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
396		printf("\nExpander @ 0x%02x read FAILED!!!\n",
397				CFG_SYS_I2C_EXPANDER_ADDR);
398	}
399
400	buf[0] &= 0x1f;
401	buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
402	if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
403		printf("\nExpander @ 0x%02x write FAILED!!!\n",
404				CFG_SYS_I2C_EXPANDER_ADDR);
405	}
406
407	/* Set the output as high */
408	temp = REG(GPIO_BANK2_REG_SET_ADDR);
409	temp |= (0x01 << 6);
410	REG(GPIO_BANK2_REG_SET_ADDR) = temp;
411
412	/* Set the GPIO direction as output */
413	temp = REG(GPIO_BANK2_REG_DIR_ADDR);
414	temp &= ~(0x01 << 6);
415	REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
416
417	return 0;
418}
419#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
420
421/*
422 * Initializes on-board ethernet controllers.
423 */
424int board_eth_init(struct bd_info *bis)
425{
426#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
427	/* Select RMII fucntion through the expander */
428	if (rmii_hw_init())
429		printf("RMII hardware init failed!!!\n");
430#endif
431	return 0;
432}
433#endif /* CONFIG_DRIVER_TI_EMAC */
434