1# SPDX-License-Identifier: GPL-2.0+ 2# 3# Copyright (C) 2012 4# David Purdy <david.c.purdy@gmail.com> 5# 6# Based on Kirkwood support: 7# (C) Copyright 2009 8# Marvell Semiconductor <www.marvell.com> 9# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com> 10 11# Boot Media configurations (DONE) 12BOOT_FROM nand 13NAND_ECC_MODE default 14NAND_PAGE_SIZE 0x0800 15 16# SOC registers configuration using bootrom header extension 17# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 18 19# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME) 20DATA 0xffd100e0 0x1b1b1b9b 21 22#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?) 23DATA 0xffd01400 0x43000618 # DDR Configuration register 24# bit13-0: 0x200 (200 DDR2 clks refresh rate) 25# bit23-14: zero 26# bit24: 1= enable exit self refresh mode on DDR access 27# bit25: 1 required 28# bit29-26: zero 29# bit31-30: 01 30 31DATA 0xffd01404 0x34143000 # DDR Controller Control Low 32# bit 4: 0=addr/cmd in smame cycle 33# bit 5: 0=clk is driven during self refresh, we don't care for APX 34# bit 6: 0=use recommended falling edge of clk for addr/cmd 35# bit14: 0=input buffer always powered up 36# bit18: 1=cpu lock transaction enabled 37# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 38# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 39# bit30-28: 3 required 40# bit31: 0=no additional STARTBURST delay 41 42DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1) 43# bit3-0: TRAS lsbs 44# bit7-4: TRCD 45# bit11- 8: TRP 46# bit15-12: TWR 47# bit19-16: TWTR 48# bit20: TRAS msb 49# bit23-21: 0x0 50# bit27-24: TRRD 51# bit31-28: TRTP 52 53DATA 0xffd0140c 0x00000819 # DDR Timing (High) 54# bit6-0: TRFC 55# bit8-7: TR2R 56# bit10-9: TR2W 57# bit12-11: TW2W 58# bit31-13: zero required 59 60DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals) 61# bit1-0: 00, Cs0width=x16 62# bit3-2: 10, Cs0size=512Mb 63# bit5-4: 00, Cs2width=nonexistent 64# bit7-6: 00, Cs1size =nonexistent 65# bit9-8: 00, Cs2width=nonexistent 66# bit11-10: 00, Cs2size =nonexistent 67# bit13-12: 00, Cs3width=nonexistent 68# bit15-14: 00, Cs3size =nonexistent 69# bit16: 0, Cs0AddrSel 70# bit17: 0, Cs1AddrSel 71# bit18: 0, Cs2AddrSel 72# bit19: 0, Cs3AddrSel 73# bit31-20: 0 required 74 75DATA 0xffd01414 0x00000000 # DDR Open Pages Control 76# bit0: 0, OpenPage enabled 77# bit31-1: 0 required 78 79DATA 0xffd01418 0x00000000 # DDR Operation 80# bit3-0: 0x0, DDR cmd 81# bit31-4: 0 required 82 83DATA 0xffd0141c 0x00000632 # DDR Mode 84# bit2-0: 2, BurstLen=2 required 85# bit3: 0, BurstType=0 required 86# bit6-4: 4, CL=5 (<===== change to CL=3 ?) 87# bit7: 0, TestMode=0 normal 88# bit8: 0, DLL reset=0 normal 89# bit11-9: 6, auto-precharge write recovery ???????????? 90# bit12: 0, PD must be zero 91# bit31-13: 0 required 92 93DATA 0xffd01420 0x00000040 # DDR Extended Mode 94# bit0: 0, DDR DLL enabled 95# bit1: 0, DDR drive strenght normal 96# bit2: 0, DDR ODT control lsd (disabled) 97# bit5-3: 000, required 98# bit6: 1, DDR ODT control msb, (disabled) 99# bit9-7: 000, required 100# bit10: 0, differential DQS enabled 101# bit11: 0, required 102# bit12: 0, DDR output buffer enabled 103# bit31-13: 0 required 104 105DATA 0xffd01424 0x0000F07F # DDR Controller Control High 106# bit2-0: 111, required 107# bit3 : 1 , MBUS Burst Chop disabled 108# bit6-4: 111, required 109# bit7 : 0 110# bit8 : 0 , no sample stage 111# bit9 : 0 , no half clock cycle addition to dataout 112# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 113# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 114# bit15-12: 1111 required 115# bit31-16: 0 required 116 117DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) 118DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) 119 120DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 121DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 122# bit0: 1, Window enabled 123# bit1: 0, Write Protect disabled 124# bit3-2: 00, CS0 hit selected 125# bit23-4: ones, required 126# bit31-24: 0x07, Size (i.e. 128MB) 127 128DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 129DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 130DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 131 132DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE) 133# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 134# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 135# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 136# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 137 138DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE) 139# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 140# bit3-2: 01, ODT1 active NEVER! 141# bit31-4: zero, required 142 143DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE) 144DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE) 145#bit0=1, enable DDR init upon this register write 146 147# End of Header extension 148DATA 0x0 0x0 149