1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Collabora Ltd.
4 *
5 */
6
7#include <hang.h>
8#include <init.h>
9#include <spl.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/ddr.h>
12#include <asm/arch/imx8mn_pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/mach-imx/boot_mode.h>
15#include <asm/mach-imx/gpio.h>
16#include <asm/sections.h>
17#include <dm/device.h>
18#include <dm/uclass.h>
19
20int spl_board_boot_device(enum boot_device boot_dev_spl)
21{
22	return BOOT_DEVICE_BOOTROM;
23}
24
25void spl_dram_init(void)
26{
27	ddr_init(&dram_timing);
28}
29
30void spl_board_init(void)
31{
32	struct udevice *dev;
33	int ret;
34
35	debug("Normal Boot\n");
36
37	ret = uclass_get_device_by_name(UCLASS_CLK,
38					"clock-controller@30380000",
39					&dev);
40	if (ret < 0)
41		puts("Failed to find clock node. Check device tree\n");
42}
43
44int board_early_init_f(void)
45{
46	init_uart_clk(3);
47
48	if (IS_ENABLED(CONFIG_NAND_MXS)) {
49		init_nand_clk();
50	}
51
52	return 0;
53}
54
55void board_init_f(ulong dummy)
56{
57	int ret;
58
59	/* Clear the BSS. */
60	memset(__bss_start, 0, __bss_end - __bss_start);
61
62	arch_cpu_init();
63
64	board_early_init_f();
65
66	timer_init();
67
68	ret = spl_init();
69	if (ret) {
70		debug("spl_init() failed: %d\n", ret);
71		hang();
72	}
73
74	preloader_console_init();
75
76	enable_tzc380();
77
78	/* DDR initialization */
79	spl_dram_init();
80
81	board_init_r(NULL, 0);
82}
83