1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de> 4 * Copyright (c) 2019 Bosch Thermotechnik GmbH 5 * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de> 6 */ 7 8#include <common.h> 9#include <cpu_func.h> 10#include <bootstage.h> 11#include <dm.h> 12#include <dm/platform_data/serial_mxc.h> 13#include <dm/device-internal.h> 14#include <env.h> 15#include <hang.h> 16#include <init.h> 17#include <linux/delay.h> 18#include <mmc.h> 19 20#include <asm/io.h> 21#include <asm/gpio.h> 22#include <linux/sizes.h> 23 24#include <asm/arch/clock.h> 25#include <asm/arch/crm_regs.h> 26#include <asm/arch/iomux.h> 27#include <asm/arch/mx6-pins.h> 28#include <asm/arch/sys_proto.h> 29#include <asm/mach-imx/iomux-v3.h> 30#include <asm/sections.h> 31#include <usb.h> 32#include <usb/ehci-ci.h> 33#include <fuse.h> 34 35#include <watchdog.h> 36 37DECLARE_GLOBAL_DATA_PTR; 38 39#define GPIO_ACC_PLAT_DETECT IMX_GPIO_NR(5, 9) 40#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0) 41#define GPIO_BUZZER IMX_GPIO_NR(1, 18) 42#define GPIO_LAN1_RESET IMX_GPIO_NR(4, 27) 43#define GPIO_LAN2_RESET IMX_GPIO_NR(4, 19) 44#define GPIO_LAN3_RESET IMX_GPIO_NR(4, 18) 45#define GPIO_USB_HUB_RESET IMX_GPIO_NR(5, 5) 46#define GPIO_EXP_RS485_RESET IMX_GPIO_NR(4, 16) 47#define GPIO_TOUCH_RESET IMX_GPIO_NR(1, 20) 48 49#define BOARD_INFO_MAGIC 0x19730517 50 51struct board_info { 52 int magic; 53 int board; 54 int rev; 55}; 56 57static struct board_info *detect_board(void); 58 59#define PFID_BOARD_ACC 0xe 60 61static const char * const name_board[] = { 62 [PFID_BOARD_ACC] = "ACC", 63}; 64 65#define PFID_REV_22 0x8 66#define PFID_REV_21 0x9 67#define PFID_REV_20 0xa 68#define PFID_REV_14 0xb 69#define PFID_REV_13 0xc 70#define PFID_REV_12 0xd 71#define PFID_REV_11 0xe 72#define PFID_REV_10 0xf 73 74static const char * const name_revision[] = { 75 [0 ... PFID_REV_10] = "Unknown", 76 [PFID_REV_10] = "1.0", 77 [PFID_REV_11] = "1.1", 78 [PFID_REV_12] = "1.2", 79 [PFID_REV_13] = "1.3", 80 [PFID_REV_14] = "1.4", 81 [PFID_REV_20] = "2.0", 82 [PFID_REV_21] = "2.1", 83 [PFID_REV_22] = "2.2", 84}; 85 86/* 87 * NXP Reset Default: 0x0001B0B0 88 * - Schmitt trigger input (PAD_CTL_HYS) 89 * - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP) 90 * - Pull Enabled (PAD_CTL_PUE) 91 * - Pull/Keeper Enabled (PAD_CTL_PKE) 92 * - CMOS output (No PAD_CTL_ODE) 93 * - Medium Speed (PAD_CTL_SPEED_MED) 94 * - 40 Ohm drive strength (PAD_CTL_DSE_40ohm) 95 * - Slow (PAD_CTL_SRE_SLOW) 96 */ 97 98/* Input, no pull up/down: 0x0x000100B0 */ 99#define GPIN_PAD_CTRL (PAD_CTL_HYS \ 100 | PAD_CTL_SPEED_MED \ 101 | PAD_CTL_DSE_40ohm \ 102 | PAD_CTL_SRE_SLOW) 103 104/* Input, pull up: 0x0x0001B0B0 */ 105#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \ 106 | PAD_CTL_PUS_100K_UP \ 107 | PAD_CTL_PUE \ 108 | PAD_CTL_PKE \ 109 | PAD_CTL_SPEED_MED \ 110 | PAD_CTL_DSE_40ohm \ 111 | PAD_CTL_SRE_SLOW) 112 113/* Input, pull down: 0x0x000130B0 */ 114#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \ 115 | PAD_CTL_PUS_100K_DOWN \ 116 | PAD_CTL_PUE \ 117 | PAD_CTL_PKE \ 118 | PAD_CTL_SPEED_MED \ 119 | PAD_CTL_DSE_40ohm \ 120 | PAD_CTL_SRE_SLOW) 121 122static const iomux_v3_cfg_t board_detect_pads[] = { 123 /* Platform detect */ 124 IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 125 /* RAM Volt detect */ 126 IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 127 /* PFID 0..9 */ 128 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 129 IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 130 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 131 IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 132 IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 133 IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 134 IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 135 IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 136 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 137 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 138 /* Manufacturer */ 139 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)), 140 /* Redundant */ 141 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL)) 142}; 143 144static int gpio_acc_pfid[] = { 145 IMX_GPIO_NR(2, 0), 146 IMX_GPIO_NR(2, 1), 147 IMX_GPIO_NR(2, 2), 148 IMX_GPIO_NR(2, 3), 149 IMX_GPIO_NR(2, 4), 150 IMX_GPIO_NR(6, 14), 151 IMX_GPIO_NR(6, 15), 152 IMX_GPIO_NR(2, 5), 153 IMX_GPIO_NR(2, 6), 154 IMX_GPIO_NR(2, 7), 155 IMX_GPIO_NR(6, 16), 156 IMX_GPIO_NR(5, 4), 157}; 158 159static int init_gpio(int nr) 160{ 161 int ret; 162 163 ret = gpio_request(nr, ""); 164 if (ret != 0) { 165 printf("Could not request gpio nr: %d\n", nr); 166 hang(); 167 } 168 ret = gpio_direction_input(nr); 169 if (ret != 0) { 170 printf("Could not set gpio nr: %d to input\n", nr); 171 hang(); 172 } 173 return 0; 174} 175 176/* 177 * We want to detect the board type only once in SPL, 178 * so we store the board_info struct at beginning in IRAM. 179 * 180 * U-Boot itself can read it also, and do not need again 181 * to detect board type. 182 * 183 */ 184static struct board_info *detect_board(void) 185{ 186 struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR; 187 int i; 188 189 if (binfo->magic == BOARD_INFO_MAGIC) 190 return binfo; 191 192 puts("Board: "); 193 SETUP_IOMUX_PADS(board_detect_pads); 194 init_gpio(GPIO_ACC_PLAT_DETECT); 195 if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) { 196 puts("not supported"); 197 hang(); 198 } else { 199 puts("Bosch "); 200 } 201 202 for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++) 203 init_gpio(gpio_acc_pfid[i]); 204 205 binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 | 206 gpio_get_value(gpio_acc_pfid[1]) << 1 | 207 gpio_get_value(gpio_acc_pfid[2]) << 2 | 208 gpio_get_value(gpio_acc_pfid[11]) << 3; 209 printf("%s ", name_board[binfo->board]); 210 211 binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 | 212 gpio_get_value(gpio_acc_pfid[8]) << 1 | 213 gpio_get_value(gpio_acc_pfid[9]) << 2 | 214 gpio_get_value(gpio_acc_pfid[10]) << 3; 215 printf("rev: %s\n", name_revision[binfo->rev]); 216 217 binfo->magic = BOARD_INFO_MAGIC; 218 219 return binfo; 220} 221 222static void unset_early_gpio(void) 223{ 224 init_gpio(GPIO_LAN1_RESET); 225 init_gpio(GPIO_LAN2_RESET); 226 init_gpio(GPIO_LAN3_RESET); 227 init_gpio(GPIO_USB_HUB_RESET); 228 init_gpio(GPIO_EXP_RS485_RESET); 229 init_gpio(GPIO_TOUCH_RESET); 230 231 gpio_set_value(GPIO_LAN1_RESET, 1); 232 gpio_set_value(GPIO_LAN2_RESET, 1); 233 gpio_set_value(GPIO_LAN3_RESET, 1); 234 gpio_set_value(GPIO_USB_HUB_RESET, 1); 235 gpio_set_value(GPIO_EXP_RS485_RESET, 1); 236 gpio_set_value(GPIO_TOUCH_RESET, 1); 237} 238 239int board_late_init(void) 240{ 241 struct board_info *binfo = detect_board(); 242 243 switch (binfo->board) { 244 case PFID_BOARD_ACC: 245 env_set("bootconf", "conf-imx6q-bosch-acc.dtb"); 246 break; 247 default: 248 printf("Unknown board %d\n", binfo->board); 249 break; 250 } 251 252 unset_early_gpio(); 253 254 return 0; 255} 256 257int board_init(void) 258{ 259 /* Address of boot parameters */ 260 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 261 262 return 0; 263} 264 265int dram_init(void) 266{ 267 gd->ram_size = imx_ddr_size(); 268 269 return 0; 270} 271 272#if IS_ENABLED(CONFIG_SPL_BUILD) 273#include <asm/arch/crm_regs.h> 274#include <asm/arch/imx-regs.h> 275#include <asm/arch/iomux.h> 276#include <asm/arch/mx6-ddr.h> 277#include <asm/arch/mx6-pins.h> 278#include <asm/arch/sys_proto.h> 279#include <spl.h> 280 281/* Early 282 * - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an 283 * external pull-down resistor) 284 * - Touch clean reset on every boot 285 * - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init 286 */ 287static const iomux_v3_cfg_t early_pads[] = { 288 IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */ 289 IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */ 290 IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */ 291 IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */ 292 IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */ 293 IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */ 294 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */ 295}; 296 297static void setup_iomux_early(void) 298{ 299 SETUP_IOMUX_PADS(early_pads); 300} 301 302static void set_early_gpio(void) 303{ 304 init_gpio(GPIO_BUZZER); 305 init_gpio(GPIO_LAN1_RESET); 306 init_gpio(GPIO_LAN2_RESET); 307 init_gpio(GPIO_LAN3_RESET); 308 init_gpio(GPIO_USB_HUB_RESET); 309 init_gpio(GPIO_EXP_RS485_RESET); 310 init_gpio(GPIO_TOUCH_RESET); 311 312 /* Reset signals are active low */ 313 gpio_set_value(GPIO_BUZZER, 0); 314 gpio_set_value(GPIO_LAN1_RESET, 0); 315 gpio_set_value(GPIO_LAN2_RESET, 0); 316 gpio_set_value(GPIO_LAN3_RESET, 0); 317 gpio_set_value(GPIO_USB_HUB_RESET, 0); 318 gpio_set_value(GPIO_EXP_RS485_RESET, 0); 319 gpio_set_value(GPIO_TOUCH_RESET, 0); 320} 321 322/* UART */ 323#define UART_PAD_CTRL \ 324 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 325 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 326 327#undef UART_PAD_CTRL 328#define UART_PAD_CTRL 0x1b0b1 329static const iomux_v3_cfg_t uart2_pads[] = { 330 IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 331 IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 332 IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), 333 IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), 334}; 335 336static void setup_iomux_uart(void) 337{ 338 SETUP_IOMUX_PADS(uart2_pads); 339} 340 341void spl_board_init(void) 342{ 343} 344 345static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = { 346 .dram_sdclk_0 = 0x00008038, 347 .dram_sdclk_1 = 0x00008038, 348 .dram_cas = 0x00008028, 349 .dram_ras = 0x00008028, 350 .dram_reset = 0x00000028, 351 .dram_sdcke0 = 0x00003000, 352 .dram_sdcke1 = 0x00003000, 353 .dram_sdba2 = 0x00008000, 354 .dram_sdodt0 = 0x00000028, 355 .dram_sdodt1 = 0x00000028, 356 .dram_sdqs0 = 0x00008038, 357 .dram_sdqs1 = 0x00008038, 358 .dram_sdqs2 = 0x00008038, 359 .dram_sdqs3 = 0x00008038, 360 .dram_sdqs4 = 0x00008038, 361 .dram_sdqs5 = 0x00008038, 362 .dram_sdqs6 = 0x00008038, 363 .dram_sdqs7 = 0x00008038, 364 .dram_dqm0 = 0x00008038, 365 .dram_dqm1 = 0x00008038, 366 .dram_dqm2 = 0x00008038, 367 .dram_dqm3 = 0x00008038, 368 .dram_dqm4 = 0x00008038, 369 .dram_dqm5 = 0x00008038, 370 .dram_dqm6 = 0x00008038, 371 .dram_dqm7 = 0x00008038, 372}; 373 374static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = { 375 .grp_ddr_type = 0x000C0000, 376 .grp_ddrmode_ctl = 0x00020000, 377 .grp_ddrpke = 0x00000000, 378 .grp_addds = 0x00000030, 379 .grp_ctlds = 0x00000028, 380 .grp_ddrmode = 0x00020000, 381 .grp_b0ds = 0x00000038, 382 .grp_b1ds = 0x00000038, 383 .grp_b2ds = 0x00000038, 384 .grp_b3ds = 0x00000038, 385 .grp_b4ds = 0x00000038, 386 .grp_b5ds = 0x00000038, 387 .grp_b6ds = 0x00000038, 388 .grp_b7ds = 0x00000038, 389}; 390 391static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = { 392 .p0_mpwldectrl0 = 0x0020001F, 393 .p0_mpwldectrl1 = 0x00280021, 394 .p1_mpwldectrl0 = 0x00120028, 395 .p1_mpwldectrl1 = 0x000D001F, 396 .p0_mpdgctrl0 = 0x43340342, 397 .p0_mpdgctrl1 = 0x03300325, 398 .p1_mpdgctrl0 = 0x4334033E, 399 .p1_mpdgctrl1 = 0x03280270, 400 .p0_mprddlctl = 0x46373B3E, 401 .p1_mprddlctl = 0x3B383544, 402 .p0_mpwrdlctl = 0x36383E40, 403 .p1_mpwrdlctl = 0x4030433A, 404}; 405 406/* Micron MT41K128M16JT-125 (standard - 1600,CL=11) 407 * !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!! 408 * So this setting is actually invalid! 409 * 410static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = { 411 .mem_speed = 1600, 412 .density = 2, 413 .width = 16, 414 .banks = 8, 415 .rowaddr = 14, 416 .coladdr = 10, 417 .pagesz = 2, 418 .trcd = 1375, 419 .trcmin = 4875, 420 .trasmin = 3500, 421 .SRT = 0, 422}; 423 */ 424 425/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E) 426 * Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss 427 * width set to 64, as four chips are used on acc (4 * 16 = 64) 428 */ 429static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = { 430 .mem_speed = 1066, 431 .density = 2, 432 .width = 64, 433 .banks = 8, 434 .rowaddr = 14, 435 .coladdr = 10, 436 .pagesz = 2, 437 .trcd = 1313, // 13.125ns 438 .trcmin = 5063, // 50.625ns 439 .trasmin = 3750, // 37.5ns 440 .SRT = 0, // Set to 1 for temperatures above 85 deg C 441}; 442 443static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = { 444 .ddr_type = DDR_TYPE_DDR3, 445 /* width of data bus:0=16,1=32,2=64 */ 446 .dsize = 2, 447 .cs_density = 32, /* 32Gb per CS */ 448 .ncs = 1, /* single chip select */ 449 .cs1_mirror = 0, 450 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ 451 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ 452 .walat = 0, /* Write additional latency */ 453 .ralat = 5, /* Read additional latency */ 454 .mif3_mode = 3, /* Command prediction working mode */ 455 .bi_on = 1, /* Bank interleaving enabled */ 456 .sde_to_rst = 0x33, /* 14 cycles, 200us (JEDEC default) */ 457 .rst_to_cke = 0x33, /* 33 cycles, 500us (JEDEC default) */ 458}; 459 460#define ACC_SPREAD_SPECTRUM_STOP 0x0fa 461#define ACC_SPREAD_SPECTRUM_STEP 0x001 462#define ACC_SPREAD_SPECTRUM_DENOM 0x190 463 464static void ccgr_init(void) 465{ 466 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 467 468 /* Turn clocks on/off */ 469 writel(0x00C0000F, &ccm->CCGR0); 470 writel(0x0030FC00, &ccm->CCGR1); 471 writel(0x03FF0033, &ccm->CCGR2); 472 writel(0x3FF3300F, &ccm->CCGR3); 473 writel(0x0003C300, &ccm->CCGR4); 474 writel(0x0F3000C3, &ccm->CCGR5); 475 writel(0x00000FFF, &ccm->CCGR6); 476 477 /* Enable spread spectrum */ 478 writel(BM_ANADIG_PLL_528_SS_ENABLE | 479 BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) | 480 BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP), 481 &ccm->analog_pll_528_ss); 482 483 writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM), 484 &ccm->analog_pll_528_denom); 485} 486 487/* MMC board initialization is needed till adding DM support in SPL */ 488#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC) 489#include <mmc.h> 490#include <fsl_esdhc_imx.h> 491 492static const iomux_v3_cfg_t usdhc2_pads[] = { 493 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)), 494 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)), 495 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)), 496 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)), 497 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)), 498 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)), 499 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)), /* CD */ 500}; 501 502static const iomux_v3_cfg_t usdhc4_pads[] = { 503 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)), 504 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)), 505 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)), 506 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)), 507 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)), 508 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)), 509 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)), 510 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)), 511 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)), 512 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)), 513}; 514 515struct fsl_esdhc_cfg usdhc_cfg[2] = { 516 {USDHC2_BASE_ADDR, 1, 4}, 517 {USDHC4_BASE_ADDR, 1, 8}, 518}; 519 520#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 521 522int board_mmc_getcd(struct mmc *mmc) 523{ 524 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 525 int ret = 0; 526 527 detect_board(); 528 529 switch (cfg->esdhc_base) { 530 case USDHC2_BASE_ADDR: 531 return !gpio_get_value(USDHC2_CD_GPIO); 532 case USDHC4_BASE_ADDR: 533 return 1; /* eMMC always present */ 534 } 535 536 return ret; 537} 538 539int board_mmc_init(struct bd_info *bis) 540{ 541 int i, ret; 542 543 gpio_direction_input(USDHC2_CD_GPIO); 544 /* 545 * According to the board_mmc_init() the following map is done: 546 * (U-Boot device node) (Physical Port) 547 * mmc0 USDHC2 548 * mmc1 USDHC4 549 */ 550 for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { 551 switch (i) { 552 case 0: 553 SETUP_IOMUX_PADS(usdhc2_pads); 554 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 555 break; 556 case 1: 557 SETUP_IOMUX_PADS(usdhc4_pads); 558 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 559 break; 560 default: 561 printf("Warning - USDHC%d controller not supporting\n", 562 i + 1); 563 return 0; 564 } 565 566 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 567 if (ret) { 568 printf("Warning: failed to initialize mmc dev %d\n", i); 569 return ret; 570 } 571 } 572 573 return 0; 574} 575#endif 576 577void board_boot_order(u32 *spl_boot_list) 578{ 579 u32 bmode = imx6_src_get_boot_mode(); 580 u8 boot_dev = BOOT_DEVICE_MMC1; 581 582 detect_board(); 583 584 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { 585 case IMX6_BMODE_SD: 586 case IMX6_BMODE_ESD: 587 /* SD/eSD - BOOT_DEVICE_MMC1 */ 588 if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) { 589 /* 590 * boot from SD is not allowed, if boot from eMMC is 591 * configured. 592 */ 593 puts("SD boot not allowed\n"); 594 spl_boot_list[0] = BOOT_DEVICE_NONE; 595 return; 596 } 597 598 boot_dev = BOOT_DEVICE_MMC1; 599 break; 600 601 case IMX6_BMODE_MMC: 602 case IMX6_BMODE_EMMC: 603 /* MMC/eMMC */ 604 boot_dev = BOOT_DEVICE_MMC2; 605 break; 606 default: 607 /* Default - BOOT_DEVICE_MMC1 */ 608 printf("Wrong board boot order\n"); 609 break; 610 } 611 612 spl_boot_list[0] = boot_dev; 613} 614 615static void setup_ddr(void) 616{ 617 struct board_info *binfo = detect_board(); 618 619 switch (binfo->rev) { 620 case PFID_REV_20: 621 case PFID_REV_21: 622 case PFID_REV_22: 623 default: 624 /* Rev 2 board has i.MX6 Dual with 64-bit RAM */ 625 mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width, 626 &acc_mx6d_ddr_ioregs, 627 &acc_mx6d_grp_ioregs); 628 mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib, 629 &acc_mx6d_mem_ddr3_1066); 630 /* Perform DDR DRAM calibration */ 631 udelay(100); 632 mmdc_do_write_level_calibration(&acc_mx6d_ddr_info); 633 mmdc_do_dqs_calibration(&acc_mx6d_ddr_info); 634 break; 635 } 636} 637 638void board_init_f(ulong dummy) 639{ 640 /* setup AIPS and disable watchdog power-down counter (only enabled after reset) */ 641 arch_cpu_init(); 642 643 ccgr_init(); 644 gpr_init(); 645 646 /* setup GP timer */ 647 timer_init(); 648 649 /* Enable device tree and early DM support*/ 650 spl_early_init(); 651 652 /* Setup early required pinmuxes */ 653 setup_iomux_early(); 654 set_early_gpio(); 655 656 /* Setup UART pinmux */ 657 setup_iomux_uart(); 658 659 /* UART clocks enabled and gd valid - init serial console */ 660 preloader_console_init(); 661 662 setup_ddr(); 663 664 /* Clear the BSS. */ 665 memset(__bss_start, 0, __bss_end - __bss_start); 666 667 /* load/boot image from boot device */ 668 board_init_r(NULL, 0); 669} 670#endif 671 672#if IS_ENABLED(CONFIG_USB_EHCI_MX6) 673#define USB_OTHERREGS_OFFSET 0x800 674#define UCTRL_PWR_POL BIT(9) 675 676int board_usb_phy_mode(int port) 677{ 678 if (port == 1) 679 return USB_INIT_HOST; 680 else 681 return usb_phy_mode(port); 682} 683 684int board_ehci_hcd_init(int port) 685{ 686 u32 *usbnc_usb_ctrl; 687 688 if (port > 1) 689 return -EINVAL; 690 691 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 692 port * 4); 693 694 /* Set Power polarity */ 695 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 696 697 return 0; 698} 699#endif 700 701int board_fit_config_name_match(const char *name) 702{ 703 if (!strcmp(name, "imx6q-bosch-acc")) 704 return 0; 705 return -1; 706} 707 708void reset_cpu(void) 709{ 710 puts("Hanging CPU for watchdog reset!\n"); 711 hang(); 712} 713 714#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS) 715void show_boot_progress(int val) 716{ 717 u32 fuseval; 718 int ret; 719 720 if (val < 0) 721 val *= -1; 722 723 switch (val) { 724 case BOOTSTAGE_ID_ENTER_CLI_LOOP: 725 printf("autoboot failed, check fuse\n"); 726 ret = fuse_read(0, 6, &fuseval); 727 if (ret == 0 && (fuseval & 0x2) == 0x0) { 728 printf("Enter cmdline, as device not closed\n"); 729 return; 730 } 731 ret = fuse_read(5, 7, &fuseval); 732 if (ret == 0 && fuseval == 0x0) { 733 printf("Enter cmdline, as it is a Development device\n"); 734 return; 735 } 736 panic("do not enter cmdline"); 737 break; 738 } 739} 740#endif 741