1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
6 */
7#include <config.h>
8#include <cpu_func.h>
9#include <dm.h>
10#include <init.h>
11#include <malloc.h>
12#include <errno.h>
13#include <net.h>
14#include <netdev.h>
15#include <asm/global_data.h>
16#include <asm/io.h>
17#include <linux/compiler.h>
18#include <linux/sizes.h>
19#include <dm/platform_data/serial_pl01x.h>
20#include "pcie.h"
21#include <asm/armv8/mmu.h>
22#ifdef CONFIG_VIRTIO_NET
23#include <virtio_types.h>
24#include <virtio.h>
25#endif
26
27DECLARE_GLOBAL_DATA_PTR;
28
29static const struct pl01x_serial_plat serial_plat = {
30	.base = V2M_UART0,
31	.type = TYPE_PL011,
32	.clock = CFG_PL011_CLOCK,
33};
34
35U_BOOT_DRVINFO(vexpress_serials) = {
36	.name = "serial_pl01x",
37	.plat = &serial_plat,
38};
39
40static struct mm_region vexpress64_mem_map[] = {
41	{
42		.virt = V2M_PA_BASE,
43		.phys = V2M_PA_BASE,
44		.size = SZ_2G,
45		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46			 PTE_BLOCK_NON_SHARE |
47			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48	}, {
49		.virt = V2M_DRAM_BASE,
50		.phys = V2M_DRAM_BASE,
51		.size = SZ_2G,
52		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
53			 PTE_BLOCK_INNER_SHARE
54	}, {
55		/*
56		 * DRAM beyond 2 GiB is located high. Let's map just some
57		 * of it, although U-Boot won't realistically use it, and
58		 * the actual available amount might be smaller on the model.
59		 */
60		.virt = 0x880000000UL,		/* 32 + 2 GiB */
61		.phys = 0x880000000UL,
62		.size = 6UL * SZ_1G,
63		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
64			 PTE_BLOCK_INNER_SHARE
65	}, {
66		/* List terminator */
67		0,
68	}
69};
70
71struct mm_region *mem_map = vexpress64_mem_map;
72
73/* This function gets replaced by platforms supporting PCIe.
74 * The replacement function, eg. on Juno, initialises the PCIe bus.
75 */
76__weak void vexpress64_pcie_init(void)
77{
78}
79
80int board_init(void)
81{
82	vexpress64_pcie_init();
83#ifdef CONFIG_VIRTIO_NET
84	virtio_init();
85#endif
86	return 0;
87}
88
89int dram_init(void)
90{
91	return fdtdec_setup_mem_size_base();
92}
93
94int dram_init_banksize(void)
95{
96	return fdtdec_setup_memory_banksize();
97}
98
99/* Assigned in lowlevel_init.S
100 * Push the variable into the .data section so that it
101 * does not get cleared later.
102 */
103unsigned long __section(".data") prior_stage_fdt_address[2];
104
105#ifdef CONFIG_OF_BOARD
106
107#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
108#define JUNO_FLASH_SEC_SIZE	(256 * 1024)
109static phys_addr_t find_dtb_in_nor_flash(const char *partname)
110{
111	phys_addr_t sector = CFG_SYS_FLASH_BASE;
112	int i;
113
114	for (i = 0;
115	     i < CONFIG_SYS_MAX_FLASH_SECT;
116	     i++, sector += JUNO_FLASH_SEC_SIZE) {
117		int len = strlen(partname) + 1;
118		int offs;
119		phys_addr_t imginfo;
120		u32 reg;
121
122		reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
123                /* This makes up the string "HSLFTOOF" flash footer */
124		if (reg != 0x464F4F54U)
125			continue;
126		reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
127                if (reg != 0x464C5348U)
128			continue;
129
130		for (offs = 0; offs < 32; offs += 4, len -= 4) {
131			reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
132			if (strncmp(partname + offs, (char *)&reg,
133			            len > 4 ? 4 : len))
134				break;
135
136			if (len > 4)
137				continue;
138
139			reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
140			imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
141			reg = readl(imginfo + 0x54);
142
143			return CFG_SYS_FLASH_BASE +
144			       reg * JUNO_FLASH_SEC_SIZE;
145		}
146	}
147
148	printf("No DTB found\n");
149
150	return ~0;
151}
152#endif
153
154/*
155 * Filter for a valid DTB, as TF-A happens to provide a pointer to some
156 * data structure using the DTB format, which we cannot use.
157 * The address of the DTB cannot be 0, in fact this is the reserved value
158 * for x1 in the kernel boot protocol.
159 * And while the nt_fw_config.dtb used by TF-A is a valid DTB structure, it
160 * does not contain the typical nodes and properties, which we test for by
161 * probing for the mandatory /memory node.
162 */
163static bool is_valid_dtb(uintptr_t dtb_ptr)
164{
165	if (dtb_ptr == 0 || fdt_magic(dtb_ptr) != FDT_MAGIC)
166		return false;
167
168	return fdt_subnode_offset((void *)dtb_ptr, 0, "memory") >= 0;
169}
170
171void *board_fdt_blob_setup(int *err)
172{
173#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
174	phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
175
176	*err = 0;
177	if (fdt_rom_addr == ~0UL) {
178		*err = -ENXIO;
179		return NULL;
180	}
181
182	return (void *)fdt_rom_addr;
183#endif
184
185#ifdef VEXPRESS_FDT_ADDR
186	if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) {
187		*err = 0;
188		return (void *)VEXPRESS_FDT_ADDR;
189	}
190#endif
191
192	if (is_valid_dtb(prior_stage_fdt_address[1])) {
193		*err = 0;
194		return (void *)prior_stage_fdt_address[1];
195	} else if (is_valid_dtb(prior_stage_fdt_address[0])) {
196		*err = 0;
197		return (void *)prior_stage_fdt_address[0];
198	}
199
200	if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) {
201		*err = 0;
202		return (void *)gd->fdt_blob;
203	}
204
205	*err = -ENXIO;
206	return NULL;
207}
208#endif
209
210/* Actual reset is done via PSCI. */
211void reset_cpu(void)
212{
213}
214
215/*
216 * Board specific ethernet initialization routine.
217 */
218int board_eth_init(struct bd_info *bis)
219{
220	int rc = 0;
221#ifndef CONFIG_DM_ETH
222#ifdef CONFIG_SMC911X
223	rc = smc911x_initialize(0, CFG_SMC911X_BASE);
224#endif
225#endif
226	return rc;
227}
228