1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Board specific setup info
4 *
5 * (C) Copyright 2004, ARM Ltd.
6 * Philippe Robin, <philippe.robin@arm.com>
7 */
8
9#include <config.h>
10#include <armcoremodule.h>
11
12	/* Reset using CM control register */
13.global reset_cpu
14reset_cpu:
15	mov	r0, #CM_BASE
16	ldr	r1,[r0,#OS_CTRL]
17	orr	r1,r1,#CMMASK_RESET
18	str	r1,[r0,#OS_CTRL]
19
20reset_failed:
21	b	reset_failed
22
23/* Set up the platform, once the cpu has been initialized */
24.globl lowlevel_init
25lowlevel_init:
26	/* If U-Boot has been run after the ARM boot monitor
27	 * then all the necessary actions have been done
28	 * otherwise we are running from user flash mapped to 0x00000000
29	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
30	 * Changes to the (possibly soft) reset defaults of the processor
31	 * itself should be performed in cpu/arm<>/start.S
32	 * This function affects only the core module or board settings
33	 */
34
35#ifdef CONFIG_CM_INIT
36	/* CM has an initialization register
37	 * - bits in it are wired into test-chip pins to force
38	 *   reset defaults
39	 * - may need to change its contents for U-Boot
40	 */
41
42	/* set the desired CM specific value */
43	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
44
45#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
46     !defined (CONFIG_CM940T)
47
48#ifdef	CONFIG_CM_MULTIPLE_SSRAM
49	/* set simple mapping			*/
50	and	r2,r2,#CMMASK_MAP_SIMPLE
51#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
52
53#ifdef	CONFIG_CM_TCRAM
54	/* disable TCRAM			*/
55	and	r2,r2,#CMMASK_TCRAM_DISABLE
56#endif /* #ifdef CONFIG_CM_TCRAM		*/
57
58#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
59     defined (CONFIG_CM1136JF_S)
60
61	and	r2,r2,#CMMASK_LE
62
63#endif /* cpu with little endian initialization */
64
65	orr	r2,r2,#CMMASK_CMxx6_COMMON
66
67#endif /* CMxx6 code */
68
69	/* read CM_INIT		 */
70	mov	r0, #CM_BASE
71	ldr	r1, [r0, #OS_INIT]
72	/* check against desired bit setting */
73	and	r3,r1,r2
74	cmp	r3,r2
75	beq	init_reg_OK
76
77	/* lock for change */
78	mov	r3, #CMVAL_LOCK1
79	add	r3,r3,#CMVAL_LOCK2
80	str	r3, [r0, #OS_LOCK]
81	/* set desired value */
82	orr	r1,r1,r2
83	/* write & relock CM_INIT */
84	str	r1, [r0, #OS_INIT]
85	mov	r1, #CMVAL_UNLOCK
86	str	r1, [r0, #OS_LOCK]
87
88	/* soft reset so new values used */
89	b	reset_cpu
90
91init_reg_OK:
92
93#endif /* CONFIG_CM_INIT */
94
95	mov	pc, lr
96
97#ifdef	CONFIG_CM_SPD_DETECT
98	/* Fast memory is available for the DRAM data
99	 * - ensure it has been transferred, then summarize the data
100	 *   into a CM register
101	 */
102.globl dram_query
103dram_query:
104	stmfd	r13!,{r4-r6,lr}
105	/* set up SDRAM info					*/
106	/* - based on example code from the CM User Guide */
107	mov	r0, #CM_BASE
108
109readspdbit:
110	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register	*/
111	and	r1, r1, #0x20		/* mask SPD bit (5)		*/
112	cmp	r1, #0x20		/* test if set			*/
113	bne	readspdbit
114
115setupsdram:
116	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
117	ldrb	r1, [r0, #3]		/* number of row address lines		*/
118	ldrb	r2, [r0, #4]		/* number of column address lines	*/
119	ldrb	r3, [r0, #5]		/* number of banks			*/
120	ldrb	r4, [r0, #31]		/* module bank density			*/
121	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
122	mov	r5, r5, ASL#2		/* size in MB				*/
123	mov	r0, #CM_BASE		/* reload for later code		*/
124	cmp	r5, #0x10		/* is it 16MB?				*/
125	bne	not16
126	mov	r6, #0x2		/* store size and CAS latency of 2	*/
127	b	writesize
128
129not16:
130	cmp	r5, #0x20		/* is it  32MB? */
131	bne	not32
132	mov	r6, #0x6
133	b	writesize
134
135not32:
136	cmp	r5, #0x40		/* is it  64MB? */
137	bne	not64
138	mov	r6, #0xa
139	b	writesize
140
141not64:
142	cmp	r5, #0x80		/* is it 128MB? */
143	bne	not128
144	mov	r6, #0xe
145	b	writesize
146
147not128:
148	/* if it is none of these sizes then it is either 256MB, or
149	 * there is no SDRAM fitted so default to 256MB
150	 */
151	mov	r6, #0x12
152
153writesize:
154	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
155	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
156	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
157	orr	r6, r6, r3		/* OR in size and CAS latency	 */
158	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
159
160#endif /* #ifdef CONFIG_CM_SPD_DETECT */
161
162	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
163
164#ifdef	CONFIG_CM_REMAP
165	/* CM remap bit is operational
166	 * - use it to map writeable memory at 0x00000000, in place of flash
167	 */
168.globl cm_remap
169cm_remap:
170	stmfd	r13!,{r4-r10,lr}
171
172	mov	r0, #CM_BASE
173	ldr	r1, [r0, #OS_CTRL]
174	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
175	str	r1, [r0, #OS_CTRL]
176
177	/* Now 0x00000000 is writeable, replace the vectors	*/
178	ldr	r0, =_start	/* r0 <- start of vectors	*/
179	add	r2, r0, #64	/* r2 <- past vectors	*/
180	sub	r1,r1,r1		/* destination 0x00000000	*/
181
182copy_vec:
183	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
184	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
185	cmp	r0, r2			/* until source end address [r2]	*/
186	ble	copy_vec
187
188	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
189
190#endif /* #ifdef CONFIG_CM_REMAP */
191