1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2021-2022  Tony Dinh <mibodhi@gmail.com>
4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 */
8
9#include <common.h>
10#include <init.h>
11#include <netdev.h>
12#include <asm/global_data.h>
13#include <asm/mach-types.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/soc.h>
16#include <asm/arch/mpp.h>
17#include <linux/bitops.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#define SHEEVAPLUG_OE_LOW		(~(0))
22#define SHEEVAPLUG_OE_HIGH		(~(0))
23#define SHEEVAPLUG_OE_VAL_LOW		BIT(29)       /* USB_PWEN low */
24#define SHEEVAPLUG_OE_VAL_HIGH		BIT(17)       /* LED pin high */
25
26int board_early_init_f(void)
27{
28	/*
29	 * default gpio configuration
30	 * There are maximum 64 gpios controlled through 2 sets of registers
31	 * the  below configuration configures mainly initial LED status
32	 */
33	mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
34			  SHEEVAPLUG_OE_VAL_HIGH,
35			  SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
36
37	/* Multi-Purpose Pins Functionality configuration */
38	static const u32 kwmpp_config[] = {
39		MPP0_NF_IO2,
40		MPP1_NF_IO3,
41		MPP2_NF_IO4,
42		MPP3_NF_IO5,
43		MPP4_NF_IO6,
44		MPP5_NF_IO7,
45		MPP6_SYSRST_OUTn,
46		MPP7_GPO,
47		MPP8_UART0_RTS,
48		MPP9_UART0_CTS,
49		MPP10_UART0_TXD,
50		MPP11_UART0_RXD,
51		MPP12_SD_CLK,
52		MPP13_SD_CMD,
53		MPP14_SD_D0,
54		MPP15_SD_D1,
55		MPP16_SD_D2,
56		MPP17_SD_D3,
57		MPP18_NF_IO0,
58		MPP19_NF_IO1,
59		MPP20_GPIO,
60		MPP21_GPIO,
61		MPP22_GPIO,
62		MPP23_GPIO,
63		MPP24_GPIO,
64		MPP25_GPIO,
65		MPP26_GPIO,
66		MPP27_GPIO,
67		MPP28_GPIO,
68		MPP29_TSMP9,
69		MPP30_GPIO,
70		MPP31_GPIO,
71		MPP32_GPIO,
72		MPP33_GPIO,
73		MPP34_GPIO,
74		MPP35_GPIO,
75		MPP36_GPIO,
76		MPP37_GPIO,
77		MPP38_GPIO,
78		MPP39_GPIO,
79		MPP40_GPIO,
80		MPP41_GPIO,
81		MPP42_GPIO,
82		MPP43_GPIO,
83		MPP44_GPIO,
84		MPP45_GPIO,
85		MPP46_GPIO,
86		MPP47_GPIO,
87		MPP48_GPIO,
88		MPP49_GPIO,
89		0
90	};
91	kirkwood_mpp_conf(kwmpp_config, NULL);
92	return 0;
93}
94
95int board_eth_init(struct bd_info *bis)
96{
97	return cpu_eth_init(bis);
98}
99
100int board_init(void)
101{
102	/*
103	 * arch number of board
104	 */
105	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
106
107	/* address of boot parameters */
108	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
109
110	return 0;
111}
112