1// SPDX-License-Identifier: Intel 2/* 3 * Copyright (C) 2015-2016 Intel Corp. 4 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) 5 * 6 * Mostly taken from coreboot fsp2_0/silicon_init.c 7 */ 8 9#define LOG_CATEGORY UCLASS_NORTHBRIDGE 10 11#include <common.h> 12#include <binman.h> 13#include <bootstage.h> 14#include <dm.h> 15#include <log.h> 16#include <asm/arch/fsp/fsp_configs.h> 17#include <asm/arch/fsp/fsp_s_upd.h> 18#include <asm/fsp/fsp_infoheader.h> 19#include <asm/fsp2/fsp_internal.h> 20#include <asm/global_data.h> 21 22int fsp_silicon_init(bool s3wake, bool use_spi_flash) 23{ 24 struct fsps_upd upd, *fsp_upd; 25 fsp_silicon_init_func func; 26 struct fsp_header *hdr; 27 struct binman_entry entry; 28 struct udevice *dev; 29 ulong rom_offset = 0; 30 u32 init_addr; 31 int ret; 32 33 log_debug("Locating FSP\n"); 34 ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr, 35 &rom_offset); 36 if (ret) 37 return log_msg_ret("locate FSP", ret); 38 binman_set_rom_offset(rom_offset); 39 gd->arch.fsp_s_hdr = hdr; 40 41 /* Copy over the default config */ 42 fsp_upd = (struct fsps_upd *)(hdr->img_base + hdr->cfg_region_off); 43 if (fsp_upd->header.signature != FSPS_UPD_SIGNATURE) 44 return log_msg_ret("Bad UPD signature", -EPERM); 45 memcpy(&upd, fsp_upd, sizeof(upd)); 46 47 ret = fsps_update_config(dev, rom_offset, &upd); 48 if (ret) 49 return log_msg_ret("Could not setup config", ret); 50 log_debug("Silicon init @ %x...", init_addr); 51 bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s"); 52 func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init); 53 ret = func(&upd); 54 bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_S); 55 if (ret) 56 return log_msg_ret("Silicon init fail\n", ret); 57 log_debug("done\n"); 58 59 return 0; 60} 61