1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
7#include <malloc.h>
8#include <net.h>
9#include <vesa.h>
10#include <acpi/acpi_s3.h>
11#include <asm/coreboot_tables.h>
12#include <asm/e820.h>
13#include <asm/global_data.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17int high_table_reserve(void)
18{
19	/* adjust stack pointer to reserve space for configuration tables */
20	gd->arch.high_table_limit = gd->start_addr_sp;
21	gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
22	gd->arch.high_table_ptr = gd->start_addr_sp;
23
24	/* clear the memory */
25	if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
26	    gd->arch.prev_sleep_state != ACPI_S3) {
27		memset((void *)gd->arch.high_table_ptr, 0,
28		       CONFIG_HIGH_TABLE_SIZE);
29	}
30
31	gd->start_addr_sp &= ~0xf;
32
33	return 0;
34}
35
36void *high_table_malloc(size_t bytes)
37{
38	u32 new_ptr;
39	void *ptr;
40
41	new_ptr = gd->arch.high_table_ptr + bytes;
42	if (new_ptr >= gd->arch.high_table_limit)
43		return NULL;
44	ptr = (void *)gd->arch.high_table_ptr;
45	gd->arch.high_table_ptr = new_ptr;
46
47	return ptr;
48}
49
50/**
51 * cb_table_init() - initialize a coreboot table header
52 *
53 * This fills in the coreboot table header signature and the header bytes.
54 * Other fields are set to zero.
55 *
56 * @cbh:	coreboot table header address
57 */
58static void cb_table_init(struct cb_header *cbh)
59{
60	memset(cbh, 0, sizeof(struct cb_header));
61	memcpy(cbh->signature, "LBIO", 4);
62	cbh->header_bytes = sizeof(struct cb_header);
63}
64
65/**
66 * cb_table_add_entry() - add a coreboot table entry
67 *
68 * This increases the coreboot table entry size with added table entry length
69 * and increases entry count by 1.
70 *
71 * @cbh:	coreboot table header address
72 * @cbr:	to be added table entry address
73 * @return:	pointer to next table entry address
74 */
75static u32 cb_table_add_entry(struct cb_header *cbh, struct cb_record *cbr)
76{
77	cbh->table_bytes += cbr->size;
78	cbh->table_entries++;
79
80	return (u32)cbr + cbr->size;
81}
82
83/**
84 * cb_table_finalize() - finalize the coreboot table
85 *
86 * This calculates the checksum for all coreboot table entries as well as
87 * the checksum for the coreboot header itself.
88 *
89 * @cbh:	coreboot table header address
90 */
91static void cb_table_finalize(struct cb_header *cbh)
92{
93	struct cb_record *cbr = (struct cb_record *)(cbh + 1);
94
95	cbh->table_checksum = compute_ip_checksum(cbr, cbh->table_bytes);
96	cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes);
97}
98
99void write_coreboot_table(u32 addr, struct memory_area *cfg_tables)
100{
101	struct cb_header *cbh = (struct cb_header *)addr;
102	struct cb_record *cbr;
103	struct cb_memory *mem;
104	struct cb_memory_range *map;
105	struct e820_entry e820[32];
106	struct cb_framebuffer *fb;
107	struct vesa_mode_info *vesa;
108	int i, num;
109
110	cb_table_init(cbh);
111	cbr = (struct cb_record *)(cbh + 1);
112
113	/*
114	 * Two type of coreboot table entries are generated by us.
115	 * They are 'struct cb_memory' and 'struct cb_framebuffer'.
116	 */
117
118	/* populate memory map table */
119	mem = (struct cb_memory *)cbr;
120	mem->tag = CB_TAG_MEMORY;
121	map = mem->map;
122
123	/* first install e820 defined memory maps */
124	num = install_e820_map(ARRAY_SIZE(e820), e820);
125	for (i = 0; i < num; i++) {
126		map->start.lo = e820[i].addr & 0xffffffff;
127		map->start.hi = e820[i].addr >> 32;
128		map->size.lo = e820[i].size & 0xffffffff;
129		map->size.hi = e820[i].size >> 32;
130		map->type = e820[i].type;
131		map++;
132	}
133
134	/* then install all configuration tables */
135	while (cfg_tables->size) {
136		map->start.lo = cfg_tables->start & 0xffffffff;
137		map->start.hi = cfg_tables->start >> 32;
138		map->size.lo = cfg_tables->size & 0xffffffff;
139		map->size.hi = cfg_tables->size >> 32;
140		map->type = CB_MEM_TABLE;
141		map++;
142		num++;
143		cfg_tables++;
144	}
145	mem->size = num * sizeof(struct cb_memory_range) +
146		    sizeof(struct cb_record);
147	cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
148
149	/* populate framebuffer table if we have sane vesa info */
150	vesa = &mode_info.vesa;
151	if (vesa->x_resolution && vesa->y_resolution) {
152		fb = (struct cb_framebuffer *)cbr;
153		fb->tag = CB_TAG_FRAMEBUFFER;
154		fb->size = sizeof(struct cb_framebuffer);
155
156		fb->x_resolution = vesa->x_resolution;
157		fb->y_resolution = vesa->y_resolution;
158		fb->bits_per_pixel = vesa->bits_per_pixel;
159		fb->bytes_per_line = vesa->bytes_per_scanline;
160		fb->physical_address = vesa->phys_base_ptr;
161		fb->red_mask_size = vesa->red_mask_size;
162		fb->red_mask_pos = vesa->red_mask_pos;
163		fb->green_mask_size = vesa->green_mask_size;
164		fb->green_mask_pos = vesa->green_mask_pos;
165		fb->blue_mask_size = vesa->blue_mask_size;
166		fb->blue_mask_pos = vesa->blue_mask_pos;
167		fb->reserved_mask_size = vesa->reserved_mask_size;
168		fb->reserved_mask_pos = vesa->reserved_mask_pos;
169
170		cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
171	}
172
173	cb_table_finalize(cbh);
174}
175