1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6#ifndef _QUARK_H_ 7#define _QUARK_H_ 8 9/* Message Bus Ports */ 10#define MSG_PORT_MEM_ARBITER 0x00 11#define MSG_PORT_HOST_BRIDGE 0x03 12#define MSG_PORT_RMU 0x04 13#define MSG_PORT_MEM_MGR 0x05 14#define MSG_PORT_USB_AFE 0x14 15#define MSG_PORT_PCIE_AFE 0x16 16#define MSG_PORT_SOC_UNIT 0x31 17 18/* Port 0x00: Memory Arbiter Message Port Registers */ 19 20/* Enhanced Configuration Space */ 21#define AEC_CTRL 0x00 22 23/* Port 0x03: Host Bridge Message Port Registers */ 24 25/* Host Miscellaneous Controls 2 */ 26#define HMISC2 0x03 27 28#define HMISC2_SEGE 0x00000002 29#define HMISC2_SEGF 0x00000004 30#define HMISC2_SEGAB 0x00000010 31 32/* Host Memory I/O Boundary */ 33#define HM_BOUND 0x08 34#define HM_BOUND_LOCK 0x00000001 35 36/* Extended Configuration Space */ 37#define HEC_REG 0x09 38 39/* MTRR Registers */ 40#define MTRR_CAP 0x40 41#define MTRR_DEF_TYPE 0x41 42 43#define MTRR_FIX_64K_00000 0x42 44#define MTRR_FIX_64K_40000 0x43 45#define MTRR_FIX_16K_80000 0x44 46#define MTRR_FIX_16K_90000 0x45 47#define MTRR_FIX_16K_A0000 0x46 48#define MTRR_FIX_16K_B0000 0x47 49#define MTRR_FIX_4K_C0000 0x48 50#define MTRR_FIX_4K_C4000 0x49 51#define MTRR_FIX_4K_C8000 0x4a 52#define MTRR_FIX_4K_CC000 0x4b 53#define MTRR_FIX_4K_D0000 0x4c 54#define MTRR_FIX_4K_D4000 0x4d 55#define MTRR_FIX_4K_D8000 0x4e 56#define MTRR_FIX_4K_DC000 0x4f 57#define MTRR_FIX_4K_E0000 0x50 58#define MTRR_FIX_4K_E4000 0x51 59#define MTRR_FIX_4K_E8000 0x52 60#define MTRR_FIX_4K_EC000 0x53 61#define MTRR_FIX_4K_F0000 0x54 62#define MTRR_FIX_4K_F4000 0x55 63#define MTRR_FIX_4K_F8000 0x56 64#define MTRR_FIX_4K_FC000 0x57 65 66#define MTRR_SMRR_PHYBASE 0x58 67#define MTRR_SMRR_PHYMASK 0x59 68 69#define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n)) 70#define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n)) 71 72#ifndef __ASSEMBLY__ 73 74#include <linux/types.h> 75 76/* variable range MTRR usage */ 77enum { 78 MTRR_VAR_ROM, 79 MTRR_VAR_ESRAM, 80 MTRR_VAR_RAM 81}; 82 83#endif /* __ASSEMBLY__ */ 84 85/* Port 0x04: Remote Management Unit Message Port Registers */ 86 87/* ACPI PBLK Base Address Register */ 88#define PBLK_BA 0x70 89 90/* Control Register */ 91#define RMU_CTRL 0x71 92 93/* SPI DMA Base Address Register */ 94#define SPI_DMA_BA 0x7a 95 96/* Thermal Sensor Register */ 97#define TS_MODE 0xb0 98#define TS_TEMP 0xb1 99#define TS_TRIP 0xb2 100 101/* Port 0x05: Memory Manager Message Port Registers */ 102 103/* eSRAM Block Page Control */ 104#define ESRAM_BLK_CTRL 0x82 105#define ESRAM_BLOCK_MODE 0x10000000 106 107/* Port 0x14: USB2 AFE Unit Port Registers */ 108 109#define USB2_GLOBAL_PORT 0x4001 110#define USB2_PLL1 0x7f02 111#define USB2_PLL2 0x7f03 112#define USB2_COMPBG 0x7f04 113 114/* Port 0x16: PCIe AFE Unit Port Registers */ 115 116#define PCIE_RXPICTRL0_L0 0x2080 117#define PCIE_RXPICTRL0_L1 0x2180 118 119/* Port 0x31: SoC Unit Port Registers */ 120 121/* Thermal Sensor Config */ 122#define TS_CFG1 0x31 123#define TS_CFG2 0x32 124#define TS_CFG3 0x33 125#define TS_CFG4 0x34 126 127/* PCIe Controller Config */ 128#define PCIE_CFG 0x36 129#define PCIE_CTLR_PRI_RST 0x00010000 130#define PCIE_PHY_SB_RST 0x00020000 131#define PCIE_CTLR_SB_RST 0x00040000 132#define PCIE_PHY_LANE_RST 0x00090000 133#define PCIE_CTLR_MAIN_RST 0x00100000 134 135/* DRAM */ 136#define DRAM_BASE 0x00000000 137#define DRAM_MAX_SIZE 0x80000000 138 139/* eSRAM */ 140#define ESRAM_SIZE 0x80000 141 142/* Memory BAR Enable */ 143#define MEM_BAR_EN 0x00000001 144 145/* I/O BAR Enable */ 146#define IO_BAR_EN 0x80000000 147 148/* 64KiB of RMU binary in flash */ 149#define RMU_BINARY_SIZE 0x10000 150 151/* PCIe Root Port Configuration Registers */ 152 153#define PCIE_RP_CCFG 0xd0 154#define CCFG_UPRS (1 << 14) 155#define CCFG_UNRS (1 << 15) 156#define CCFG_UNSD (1 << 23) 157#define CCFG_UPSD (1 << 24) 158 159#define PCIE_RP_MPC2 0xd4 160#define MPC2_IPF (1 << 11) 161 162#define PCIE_RP_MBC 0xf4 163#define MBC_SBIC (3 << 16) 164 165/* Legacy Bridge PCI Configuration Registers */ 166#define LB_GBA 0x44 167#define LB_PM1BLK 0x48 168#define LB_GPE0BLK 0x4c 169#define LB_ACTL 0x58 170#define LB_PABCDRC 0x60 171#define LB_PEFGHRC 0x64 172#define LB_WDTBA 0x84 173#define LB_BCE 0xd4 174#define LB_BC 0xd8 175#define LB_RCBA 0xf0 176 177/* USB EHCI memory-mapped registers */ 178#define EHCI_INSNREG01 0x94 179 180/* USB device memory-mapped registers */ 181#define USBD_INT_MASK 0x410 182#define USBD_EP_INT_STS 0x414 183#define USBD_EP_INT_MASK 0x418 184 185#ifndef __ASSEMBLY__ 186 187/* Root Complex Register Block */ 188struct quark_rcba { 189 u32 rctl; 190 u32 esd; 191 u32 rsvd1[3150]; 192 u16 rmu_ir; 193 u16 d23_ir; 194 u16 core_ir; 195 u16 d20d21_ir; 196}; 197 198#include <asm/io.h> 199#include <asm/pci.h> 200 201/** 202 * qrk_pci_read_config_dword() - Read a configuration value 203 * 204 * @dev: PCI device address: bus, device and function 205 * @offset: Dword offset within the device's configuration space 206 * @valuep: Place to put the returned value 207 * 208 * Note: This routine is inlined to provide better performance on Quark 209 */ 210static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset, 211 u32 *valuep) 212{ 213 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 214 *valuep = inl(PCI_REG_DATA); 215} 216 217/** 218 * qrk_pci_write_config_dword() - Write a PCI configuration value 219 * 220 * @dev: PCI device address: bus, device and function 221 * @offset: Dword offset within the device's configuration space 222 * @value: Value to write 223 * 224 * Note: This routine is inlined to provide better performance on Quark 225 */ 226static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset, 227 u32 value) 228{ 229 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 230 outl(value, PCI_REG_DATA); 231} 232 233/** 234 * board_assert_perst() - Assert the PERST# pin 235 * 236 * The CPU interface to the PERST# signal on Quark is platform dependent. 237 * Board-specific codes need supply this routine to assert PCIe slot reset. 238 * 239 * The tricky part in this routine is that any APIs that may trigger PCI 240 * enumeration process are strictly forbidden, as any access to PCIe root 241 * port's configuration registers will cause system hang while it is held 242 * in reset. 243 */ 244void board_assert_perst(void); 245 246/** 247 * board_deassert_perst() - De-assert the PERST# pin 248 * 249 * The CPU interface to the PERST# signal on Quark is platform dependent. 250 * Board-specific codes need supply this routine to de-assert PCIe slot reset. 251 * 252 * The tricky part in this routine is that any APIs that may trigger PCI 253 * enumeration process are strictly forbidden, as any access to PCIe root 254 * port's configuration registers will cause system hang while it is held 255 * in reset. 256 */ 257void board_deassert_perst(void); 258 259#endif /* __ASSEMBLY__ */ 260 261#endif /* _QUARK_H_ */ 262