1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Definitions for the GPIO subsystem on Apollolake 4 * 5 * Copyright (C) 2015 - 2017 Intel Corp. 6 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) 7 * 8 * Placed in a separate file since some of these definitions can be used from 9 * assembly code 10 * 11 * Taken from gpio_apl.h in coreboot 12 */ 13 14#ifndef _ASM_ARCH_GPIO_H_ 15#define _ASM_ARCH_GPIO_H_ 16 17/* Port ids */ 18#define PID_GPIO_SW 0xC0 19#define PID_GPIO_S 0xC2 20#define PID_GPIO_W 0xC7 21#define PID_GPIO_NW 0xC4 22#define PID_GPIO_N 0xC5 23#define PID_ITSS 0xD0 24#define PID_RTC 0xD1 25 26/* 27 * Miscellaneous Configuration register(MISCCFG). These are community-specific 28 * registers and are meant to house miscellaneous configuration fields per 29 * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent) 30 */ 31#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */ 32#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */ 33#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */ 34#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */ 35#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */ 36#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */ 37#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */ 38#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */ 39#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */ 40 41#define GPIO_MAX_NUM_PER_GROUP 32 42 43/* 44 * Host Software Pad Ownership Register. 45 * The pins in the community are divided into 3 groups: 46 * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95 47 */ 48#define HOSTSW_OWN_REG_0 0x80 49 50#define PAD_CFG_BASE 0x500 51 52#define GPI_INT_STS_0 0x100 53#define GPI_INT_EN_0 0x110 54 55#define GPI_SMI_STS_0 0x140 56#define GPI_SMI_EN_0 0x150 57 58#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1) 59#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1) 60#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1) 61#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1) 62 63#define NUM_N_GPI_REGS \ 64 (ALIGN(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) 65 66#define NUM_NW_GPI_REGS \ 67 (ALIGN(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) 68 69#define NUM_W_GPI_REGS \ 70 (ALIGN(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) 71 72#define NUM_SW_GPI_REGS \ 73 (ALIGN(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) 74 75/* 76 * Total number of GPI status registers across all GPIO communities in the SOC 77 */ 78#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \ 79 + NUM_W_GPI_REGS + NUM_SW_GPI_REGS) 80 81/* North community pads */ 82#define GPIO_0 0 83#define GPIO_1 1 84#define GPIO_2 2 85#define GPIO_3 3 86#define GPIO_4 4 87#define GPIO_5 5 88#define GPIO_6 6 89#define GPIO_7 7 90#define GPIO_8 8 91#define GPIO_9 9 92#define GPIO_10 10 93#define GPIO_11 11 94#define GPIO_12 12 95#define GPIO_13 13 96#define GPIO_14 14 97#define GPIO_15 15 98#define GPIO_16 16 99#define GPIO_17 17 100#define GPIO_18 18 101#define GPIO_19 19 102#define GPIO_20 20 103#define GPIO_21 21 104#define GPIO_22 22 105#define GPIO_23 23 106#define GPIO_24 24 107#define GPIO_25 25 108#define GPIO_26 26 109#define GPIO_27 27 110#define GPIO_28 28 111#define GPIO_29 29 112#define GPIO_30 30 113#define GPIO_31 31 114#define GPIO_32 32 115#define GPIO_33 33 116#define GPIO_34 34 117#define GPIO_35 35 118#define GPIO_36 36 119#define GPIO_37 37 120#define GPIO_38 38 121#define GPIO_39 39 122#define GPIO_40 40 123#define GPIO_41 41 124#define GPIO_42 42 125#define GPIO_43 43 126#define GPIO_44 44 127#define GPIO_45 45 128#define GPIO_46 46 129#define GPIO_47 47 130#define GPIO_48 48 131#define GPIO_49 49 132#define GPIO_62 50 133#define GPIO_63 51 134#define GPIO_64 52 135#define GPIO_65 53 136#define GPIO_66 54 137#define GPIO_67 55 138#define GPIO_68 56 139#define GPIO_69 57 140#define GPIO_70 58 141#define GPIO_71 59 142#define GPIO_72 60 143#define GPIO_73 61 144#define JTAG_TCK 62 145#define JTAG_TRST_B 63 146#define JTAG_TMS 64 147#define JTAG_TDI 65 148#define JTAG_CX_PMODE 66 149#define JTAG_CX_PREQ_B 67 150#define JTAGX 68 151#define JTAG_CX_PRDY_B 69 152#define JTAG_TDO 70 153#define CNV_BRI_DT 71 154#define CNV_BRI_RSP 72 155#define CNV_RGI_DT 73 156#define CNV_RGI_RSP 74 157#define SVID0_ALERT_B 75 158#define SVID0_DATA 76 159#define SVID0_CLK 77 160 161/* Northwest community pads */ 162#define GPIO_187 78 163#define GPIO_188 79 164#define GPIO_189 80 165#define GPIO_190 81 166#define GPIO_191 82 167#define GPIO_192 83 168#define GPIO_193 84 169#define GPIO_194 85 170#define GPIO_195 86 171#define GPIO_196 87 172#define GPIO_197 88 173#define GPIO_198 89 174#define GPIO_199 90 175#define GPIO_200 91 176#define GPIO_201 92 177#define GPIO_202 93 178#define GPIO_203 94 179#define GPIO_204 95 180#define PMC_SPI_FS0 96 181#define PMC_SPI_FS1 97 182#define PMC_SPI_FS2 98 183#define PMC_SPI_RXD 99 184#define PMC_SPI_TXD 100 185#define PMC_SPI_CLK 101 186#define PMIC_PWRGOOD 102 187#define PMIC_RESET_B 103 188#define GPIO_213 104 189#define GPIO_214 105 190#define GPIO_215 106 191#define PMIC_THERMTRIP_B 107 192#define PMIC_STDBY 108 193#define PROCHOT_B 109 194#define PMIC_I2C_SCL 110 195#define PMIC_I2C_SDA 111 196#define GPIO_74 112 197#define GPIO_75 113 198#define GPIO_76 114 199#define GPIO_77 115 200#define GPIO_78 116 201#define GPIO_79 117 202#define GPIO_80 118 203#define GPIO_81 119 204#define GPIO_82 120 205#define GPIO_83 121 206#define GPIO_84 122 207#define GPIO_85 123 208#define GPIO_86 124 209#define GPIO_87 125 210#define GPIO_88 126 211#define GPIO_89 127 212#define GPIO_90 128 213#define GPIO_91 129 214#define GPIO_92 130 215#define GPIO_97 131 216#define GPIO_98 132 217#define GPIO_99 133 218#define GPIO_100 134 219#define GPIO_101 135 220#define GPIO_102 136 221#define GPIO_103 137 222#define FST_SPI_CLK_FB 138 223#define GPIO_104 139 224#define GPIO_105 140 225#define GPIO_106 141 226#define GPIO_109 142 227#define GPIO_110 143 228#define GPIO_111 144 229#define GPIO_112 145 230#define GPIO_113 146 231#define GPIO_116 147 232#define GPIO_117 148 233#define GPIO_118 149 234#define GPIO_119 150 235#define GPIO_120 151 236#define GPIO_121 152 237#define GPIO_122 153 238#define GPIO_123 154 239 240/* West community pads */ 241#define GPIO_124 155 242#define GPIO_125 156 243#define GPIO_126 157 244#define GPIO_127 158 245#define GPIO_128 159 246#define GPIO_129 160 247#define GPIO_130 161 248#define GPIO_131 162 249#define GPIO_132 163 250#define GPIO_133 164 251#define GPIO_134 165 252#define GPIO_135 166 253#define GPIO_136 167 254#define GPIO_137 168 255#define GPIO_138 169 256#define GPIO_139 170 257#define GPIO_146 171 258#define GPIO_147 172 259#define GPIO_148 173 260#define GPIO_149 174 261#define GPIO_150 175 262#define GPIO_151 176 263#define GPIO_152 177 264#define GPIO_153 178 265#define GPIO_154 179 266#define GPIO_155 180 267#define GPIO_209 181 268#define GPIO_210 182 269#define GPIO_211 183 270#define GPIO_212 184 271#define OSC_CLK_OUT_0 185 272#define OSC_CLK_OUT_1 186 273#define OSC_CLK_OUT_2 187 274#define OSC_CLK_OUT_3 188 275#define OSC_CLK_OUT_4 189 276#define PMU_AC_PRESENT 190 277#define PMU_BATLOW_B 191 278#define PMU_PLTRST_B 192 279#define PMU_PWRBTN_B 193 280#define PMU_RESETBUTTON_B 194 281#define PMU_SLP_S0_B 195 282#define PMU_SLP_S3_B 196 283#define PMU_SLP_S4_B 197 284#define PMU_SUSCLK 198 285#define PMU_WAKE_B 199 286#define SUS_STAT_B 200 287#define SUSPWRDNACK 201 288 289/* Southwest community pads */ 290#define GPIO_205 202 291#define GPIO_206 203 292#define GPIO_207 204 293#define GPIO_208 205 294#define GPIO_156 206 295#define GPIO_157 207 296#define GPIO_158 208 297#define GPIO_159 209 298#define GPIO_160 210 299#define GPIO_161 211 300#define GPIO_162 212 301#define GPIO_163 213 302#define GPIO_164 214 303#define GPIO_165 215 304#define GPIO_166 216 305#define GPIO_167 217 306#define GPIO_168 218 307#define GPIO_169 219 308#define GPIO_170 220 309#define GPIO_171 221 310#define GPIO_172 222 311#define GPIO_179 223 312#define GPIO_173 224 313#define GPIO_174 225 314#define GPIO_175 226 315#define GPIO_176 227 316#define GPIO_177 228 317#define GPIO_178 229 318#define GPIO_186 230 319#define GPIO_182 231 320#define GPIO_183 232 321#define SMB_ALERTB 233 322#define SMB_CLK 234 323#define SMB_DATA 235 324#define LPC_ILB_SERIRQ 236 325#define LPC_CLKOUT0 237 326#define LPC_CLKOUT1 238 327#define LPC_AD0 239 328#define LPC_AD1 240 329#define LPC_AD2 241 330#define LPC_AD3 242 331#define LPC_CLKRUNB 243 332#define LPC_FRAMEB 244 333 334/* PERST_0 not defined */ 335#define GPIO_PRT0_UDEF 0xFF 336 337#define TOTAL_PADS 245 338#define N_OFFSET GPIO_0 339#define NW_OFFSET GPIO_187 340#define W_OFFSET GPIO_124 341#define SW_OFFSET GPIO_205 342 343/* Macros for translating a global pad offset to a local offset */ 344#define PAD_N(pad) (pad - N_OFFSET) 345#define PAD_NW(pad) (pad - NW_OFFSET) 346#define PAD_W(pad) (pad - W_OFFSET) 347#define PAD_SW(pad) (pad - SW_OFFSET) 348 349/* Linux names of the GPIO devices */ 350#define GPIO_COMM_N_NAME "INT3452:00" 351#define GPIO_COMM_NW_NAME "INT3452:01" 352#define GPIO_COMM_W_NAME "INT3452:02" 353#define GPIO_COMM_SW_NAME "INT3452:03" 354 355/* Following is used in gpio asl */ 356#define GPIO_COMM_NAME "INT3452" 357#define GPIO_COMM_0_DESC \ 358 "General Purpose Input/Output (GPIO) Controller - North" 359#define GPIO_COMM_1_DESC \ 360 "General Purpose Input/Output (GPIO) Controller - Northwest" 361#define GPIO_COMM_2_DESC \ 362 "General Purpose Input/Output (GPIO) Controller - West" 363#define GPIO_COMM_3_DESC \ 364 "General Purpose Input/Output (GPIO) Controller - Southwest" 365 366#define GPIO_COMM0_PID PID_GPIO_N 367#define GPIO_COMM1_PID PID_GPIO_NW 368#define GPIO_COMM2_PID PID_GPIO_W 369#define GPIO_COMM3_PID PID_GPIO_SW 370 371/* 372 * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use 373 * shared IRQ instead of direct IRQ, in case of overlapping, we can easily 374 * program one of the overlap to shared IRQ to avoid the conflict. 375 */ 376 377/* NorthWest community pads */ 378#define PMIC_I2C_SDA_IRQ 0x32 379#define GPIO_74_IRQ 0x33 380#define GPIO_75_IRQ 0x34 381#define GPIO_76_IRQ 0x35 382#define GPIO_77_IRQ 0x36 383#define GPIO_78_IRQ 0x37 384#define GPIO_79_IRQ 0x38 385#define GPIO_80_IRQ 0x39 386#define GPIO_81_IRQ 0x3A 387#define GPIO_82_IRQ 0x3B 388#define GPIO_83_IRQ 0x3C 389#define GPIO_84_IRQ 0x3D 390#define GPIO_85_IRQ 0x3E 391#define GPIO_86_IRQ 0x3F 392#define GPIO_87_IRQ 0x40 393#define GPIO_88_IRQ 0x41 394#define GPIO_89_IRQ 0x42 395#define GPIO_90_IRQ 0x43 396#define GPIO_91_IRQ 0x44 397#define GPIO_97_IRQ 0x49 398#define GPIO_98_IRQ 0x4A 399#define GPIO_99_IRQ 0x4B 400#define GPIO_100_IRQ 0x4C 401#define GPIO_101_IRQ 0x4D 402#define GPIO_102_IRQ 0x4E 403#define GPIO_103_IRQ 0x4F 404#define GPIO_104_IRQ 0x50 405#define GPIO_105_IRQ 0x51 406#define GPIO_106_IRQ 0x52 407#define GPIO_109_IRQ 0x54 408#define GPIO_110_IRQ 0x55 409#define GPIO_111_IRQ 0x56 410#define GPIO_112_IRQ 0x57 411#define GPIO_113_IRQ 0x58 412#define GPIO_116_IRQ 0x5B 413#define GPIO_117_IRQ 0x5C 414#define GPIO_118_IRQ 0x5D 415#define GPIO_119_IRQ 0x5E 416#define GPIO_120_IRQ 0x5F 417#define GPIO_121_IRQ 0x60 418#define GPIO_122_IRQ 0x61 419#define GPIO_123_IRQ 0x62 420 421/* North community pads */ 422#define GPIO_0_IRQ 0x63 423#define GPIO_1_IRQ 0x64 424#define GPIO_2_IRQ 0x65 425#define GPIO_3_IRQ 0x66 426#define GPIO_4_IRQ 0x67 427#define GPIO_5_IRQ 0x68 428#define GPIO_6_IRQ 0x69 429#define GPIO_7_IRQ 0x6A 430#define GPIO_8_IRQ 0x6B 431#define GPIO_9_IRQ 0x6C 432#define GPIO_10_IRQ 0x6D 433#define GPIO_11_IRQ 0x6E 434#define GPIO_12_IRQ 0x6F 435#define GPIO_13_IRQ 0x70 436#define GPIO_14_IRQ 0x71 437#define GPIO_15_IRQ 0x72 438#define GPIO_16_IRQ 0x73 439#define GPIO_17_IRQ 0x74 440#define GPIO_18_IRQ 0x75 441#define GPIO_19_IRQ 0x76 442#define GPIO_20_IRQ 0x77 443#define GPIO_21_IRQ 0x32 444#define GPIO_22_IRQ 0x33 445#define GPIO_23_IRQ 0x34 446#define GPIO_24_IRQ 0x35 447#define GPIO_25_IRQ 0x36 448#define GPIO_26_IRQ 0x37 449#define GPIO_27_IRQ 0x38 450#define GPIO_28_IRQ 0x39 451#define GPIO_29_IRQ 0x3A 452#define GPIO_30_IRQ 0x3B 453#define GPIO_31_IRQ 0x3C 454#define GPIO_32_IRQ 0x3D 455#define GPIO_33_IRQ 0x3E 456#define GPIO_34_IRQ 0x3F 457#define GPIO_35_IRQ 0x40 458#define GPIO_36_IRQ 0x41 459#define GPIO_37_IRQ 0x42 460#define GPIO_38_IRQ 0x43 461#define GPIO_39_IRQ 0x44 462#define GPIO_40_IRQ 0x45 463#define GPIO_41_IRQ 0x46 464#define GPIO_42_IRQ 0x47 465#define GPIO_43_IRQ 0x48 466#define GPIO_44_IRQ 0x49 467#define GPIO_45_IRQ 0x4A 468#define GPIO_46_IRQ 0x4B 469#define GPIO_47_IRQ 0x4C 470#define GPIO_48_IRQ 0x4D 471#define GPIO_49_IRQ 0x4E 472#define GPIO_62_IRQ 0x5B 473#define GPIO_63_IRQ 0x5C 474#define GPIO_64_IRQ 0x5D 475#define GPIO_65_IRQ 0x5E 476#define GPIO_66_IRQ 0x5F 477#define GPIO_67_IRQ 0x60 478#define GPIO_68_IRQ 0x61 479#define GPIO_69_IRQ 0x62 480#define GPIO_70_IRQ 0x63 481#define GPIO_71_IRQ 0x64 482#define GPIO_72_IRQ 0x65 483#define GPIO_73_IRQ 0x66 484 485/* This is needed by ACPI */ 486#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ 487 488#ifndef __ASSEMBLY__ 489 490#include <dt-structs.h> 491 492/** 493 * struct apl_gpio_plat - platform data for each device 494 * 495 * @dtplat: of-platdata data from C struct 496 */ 497struct apl_gpio_plat { 498#if CONFIG_IS_ENABLED(OF_PLATDATA) 499 /* Put this first since driver model will copy the data here */ 500 struct dtd_intel_apl_pinctrl dtplat; 501#endif 502}; 503 504#endif /* __ASSEMBLY__ */ 505 506#endif /* _ASM_ARCH_GPIO_H_ */ 507