1/* SPDX-License-Identifier: Intel */ 2/* 3 * Copyright (c) 2016, Intel Corporation. All rights reserved. 4 * Copyright 2019 Google LLC 5 */ 6#ifndef __ASM_ARCH_FSP_S_UDP_H 7#define __ASM_ARCH_FSP_S_UDP_H 8 9#ifndef __ASSEMBLY__ 10#include <asm/fsp2/fsp_api.h> 11 12/** 13 * struct fsp_s_config - FSP-S configuration 14 * 15 * Note that struct fsp_upd_header preceeds this and is 32 bytes long. The 16 * hex offsets mentioned in this file are relative to the start of the header, 17 * the same convention used in Intel's APL FSP header file. 18 */ 19struct __packed fsp_s_config { 20 /* 0x20 */ 21 u8 active_processor_cores; 22 u8 disable_core1; 23 u8 disable_core2; 24 u8 disable_core3; 25 u8 vmx_enable; 26 u8 proc_trace_mem_size; 27 u8 proc_trace_enable; 28 u8 eist; 29 u8 boot_p_state; 30 u8 enable_cx; 31 u8 c1e; 32 u8 bi_proc_hot; 33 u8 pkg_c_state_limit; 34 u8 c_state_auto_demotion; 35 u8 c_state_un_demotion; 36 u8 max_core_c_state; 37 38 /* 0x30 */ 39 u8 pkg_c_state_demotion; 40 u8 pkg_c_state_un_demotion; 41 u8 turbo_mode; 42 u8 hda_verb_table_entry_num; 43 u32 hda_verb_table_ptr; 44 u8 p2sb_unhide; 45 u8 ipu_en; 46 u8 ipu_acpi_mode; 47 u8 force_wake; 48 u32 gtt_mm_adr; 49 50 /* 0x40 */ 51 u32 gm_adr; 52 u8 pavp_lock; 53 u8 graphics_freq_modify; 54 u8 graphics_freq_req; 55 u8 graphics_video_freq; 56 u8 pm_lock; 57 u8 dop_clock_gating; 58 u8 unsolicited_attack_override; 59 u8 wopcm_support; 60 u8 wopcm_size; 61 u8 power_gating; 62 u8 unit_level_clock_gating; 63 u8 fast_boot; 64 65 /* 0x50 */ 66 u8 dyn_sr; 67 u8 sa_ipu_enable; 68 u8 pm_support; 69 u8 enable_render_standby; 70 u32 logo_size; 71 u32 logo_ptr; 72 u32 graphics_config_ptr; 73 74 /* 0x60 */ 75 u8 pavp_enable; 76 u8 pavp_pr3; 77 u8 cd_clock; 78 u8 pei_graphics_peim_init; 79 u8 write_protection_enable[5]; 80 u8 read_protection_enable[5]; 81 u16 protected_range_limit[5]; 82 u16 protected_range_base[5]; 83 u8 gmm; 84 u8 clk_gating_pgcb_clk_trunk; 85 u8 clk_gating_sb; 86 u8 clk_gating_sb_clk_trunk; 87 u8 clk_gating_sb_clk_partition; 88 u8 clk_gating_core; 89 u8 clk_gating_dma; 90 u8 clk_gating_reg_access; 91 u8 clk_gating_host; 92 u8 clk_gating_partition; 93 u8 clk_gating_trunk; 94 u8 hda_enable; 95 u8 dsp_enable; 96 u8 pme; 97 98 /* 0x90 */ 99 u8 hd_audio_io_buffer_ownership; 100 u8 hd_audio_io_buffer_voltage; 101 u8 hd_audio_vc_type; 102 u8 hd_audio_link_frequency; 103 u8 hd_audio_i_disp_link_frequency; 104 u8 hd_audio_i_disp_link_tmode; 105 u8 dsp_endpoint_dmic; 106 u8 dsp_endpoint_bluetooth; 107 u8 dsp_endpoint_i2s_skp; 108 u8 dsp_endpoint_i2s_hp; 109 u8 audio_ctl_pwr_gate; 110 u8 audio_dsp_pwr_gate; 111 u8 mmt; 112 u8 hmt; 113 u8 hd_audio_pwr_gate; 114 u8 hd_audio_clk_gate; 115 116 /* 0xa0 */ 117 u32 dsp_feature_mask; 118 u32 dsp_pp_module_mask; 119 u8 bios_cfg_lock_down; 120 u8 hpet; 121 u8 hpet_bdf_valid; 122 u8 hpet_bus_number; 123 u8 hpet_device_number; 124 u8 hpet_function_number; 125 u8 io_apic_bdf_valid; 126 u8 io_apic_bus_number; 127 128 /* 0xb0 */ 129 u8 io_apic_device_number; 130 u8 io_apic_function_number; 131 u8 io_apic_entry24_119; 132 u8 io_apic_id; 133 u8 io_apic_range_select; 134 u8 ish_enable; 135 u8 bios_interface; 136 u8 bios_lock; 137 u8 spi_eiss; 138 u8 bios_lock_sw_smi_number; 139 u8 lpss_s0ix_enable; 140 u8 unused_upd_space0[1]; 141 u8 i2c_clk_gate_cfg[8]; 142 u8 hsuart_clk_gate_cfg[4]; 143 u8 spi_clk_gate_cfg[3]; 144 u8 i2c0_enable; 145 u8 i2c1_enable; 146 u8 i2c2_enable; 147 u8 i2c3_enable; 148 u8 i2c4_enable; 149 150 /* 0xd0 */ 151 u8 i2c5_enable; 152 u8 i2c6_enable; 153 u8 i2c7_enable; 154 u8 hsuart0_enable; 155 u8 hsuart1_enable; 156 u8 hsuart2_enable; 157 u8 hsuart3_enable; 158 u8 spi0_enable; 159 u8 spi1_enable; 160 u8 spi2_enable; 161 u8 os_dbg_enable; 162 u8 dci_en; 163 u32 uart2_kernel_debug_base_address; 164 165 /* 0xe0 */ 166 u8 pcie_clock_gating_disabled; 167 u8 pcie_root_port8xh_decode; 168 u8 pcie8xh_decode_port_index; 169 u8 pcie_root_port_peer_memory_write_enable; 170 u8 pcie_aspm_sw_smi_number; 171 u8 unused_upd_space1[1]; 172 u8 pcie_root_port_en[6]; 173 u8 pcie_rp_hide[6]; 174 u8 pcie_rp_slot_implemented[6]; 175 u8 pcie_rp_hot_plug[6]; 176 u8 pcie_rp_pm_sci[6]; 177 u8 pcie_rp_ext_sync[6]; 178 u8 pcie_rp_transmitter_half_swing[6]; 179 180 /* 0x110 */ 181 u8 pcie_rp_acs_enabled[6]; 182 u8 pcie_rp_clk_req_supported[6]; 183 u8 pcie_rp_clk_req_number[6]; 184 u8 pcie_rp_clk_req_detect[6]; 185 u8 advanced_error_reporting[6]; 186 u8 pme_interrupt[6]; 187 u8 unsupported_request_report[6]; 188 u8 fatal_error_report[6]; 189 190 /* 0x140 */ 191 u8 no_fatal_error_report[6]; 192 u8 correctable_error_report[6]; 193 u8 system_error_on_fatal_error[6]; 194 u8 system_error_on_non_fatal_error[6]; 195 u8 system_error_on_correctable_error[6]; 196 u8 pcie_rp_speed[6]; 197 u8 physical_slot_number[6]; 198 u8 pcie_rp_completion_timeout[6]; 199 200 /* 0x170 */ 201 u8 ptm_enable[6]; 202 u8 pcie_rp_aspm[6]; 203 u8 pcie_rp_l1_substates[6]; 204 u8 pcie_rp_ltr_enable[6]; 205 u8 pcie_rp_ltr_config_lock[6]; 206 u8 pme_b0_s5_dis; 207 u8 pci_clock_run; 208 209 /* 0x190 */ 210 u8 timer8254_clk_setting; 211 u8 enable_sata; 212 u8 sata_mode; 213 u8 sata_salp_support; 214 u8 sata_pwr_opt_enable; 215 u8 e_sata_speed_limit; 216 u8 speed_limit; 217 u8 unused_upd_space2[1]; 218 u8 sata_ports_enable[2]; 219 u8 sata_ports_dev_slp[2]; 220 u8 sata_ports_hot_plug[2]; 221 u8 sata_ports_interlock_sw[2]; 222 223 /* 0x1a0 */ 224 u8 sata_ports_external[2]; 225 u8 sata_ports_spin_up[2]; 226 u8 sata_ports_solid_state_drive[2]; 227 u8 sata_ports_enable_dito_config[2]; 228 u8 sata_ports_dm_val[2]; 229 u8 unused_upd_space3[2]; 230 u16 sata_ports_dito_val[2]; 231 232 /* 0x1b0 */ 233 u16 sub_system_vendor_id; 234 u16 sub_system_id; 235 u8 crid_settings; 236 u8 reset_select; 237 u8 sdcard_enabled; 238 u8 e_mmc_enabled; 239 u8 e_mmc_host_max_speed; 240 u8 ufs_enabled; 241 u8 sdio_enabled; 242 u8 gpp_lock; 243 u8 sirq_enable; 244 u8 sirq_mode; 245 u8 start_frame_pulse; 246 u8 smbus_enable; 247 248 /* 0x1c0 */ 249 u8 arp_enable; 250 u8 unused_upd_space4; 251 u16 num_rsvd_smbus_addresses; 252 u8 rsvd_smbus_address_table[128]; 253 u8 disable_compliance_mode; 254 u8 usb_per_port_ctl; 255 u8 usb30_mode; 256 u8 unused_upd_space5[1]; 257 u8 port_usb20_enable[8]; 258 259 /* 0x250 */ 260 u8 port_us20b_over_current_pin[8]; 261 u8 usb_otg; 262 u8 hsic_support_enable; 263 u8 port_usb30_enable[6]; 264 265 /* 0x260 */ 266 u8 port_us30b_over_current_pin[6]; 267 u8 ssic_port_enable[2]; 268 u16 dlane_pwr_gating; 269 u8 vtd_enable; 270 u8 lock_down_global_smi; 271 u16 reset_wait_timer; 272 u8 rtc_lock; 273 u8 sata_test_mode; 274 275 /* 0x270 */ 276 u8 ssic_rate[2]; 277 u16 dynamic_power_gating; 278 u16 pcie_rp_ltr_max_snoop_latency[6]; 279 280 /* 0x280 */ 281 u8 pcie_rp_snoop_latency_override_mode[6]; 282 u8 unused_upd_space6[2]; 283 u16 pcie_rp_snoop_latency_override_value[6]; 284 u8 pcie_rp_snoop_latency_override_multiplier[6]; 285 u8 skip_mp_init; 286 u8 dci_auto_detect; 287 u16 pcie_rp_ltr_max_non_snoop_latency[6]; 288 u8 pcie_rp_non_snoop_latency_override_mode[6]; 289 u8 tco_timer_halt_lock; 290 u8 pwr_btn_override_period; 291 292 /* 0x2b0 */ 293 u16 pcie_rp_non_snoop_latency_override_value[6]; 294 u8 pcie_rp_non_snoop_latency_override_multiplier[6]; 295 u8 pcie_rp_slot_power_limit_scale[6]; 296 u8 pcie_rp_slot_power_limit_value[6]; 297 u8 disable_native_power_button; 298 u8 power_butter_debounce_mode; 299 300 /* 0x2d0 */ 301 u32 sdio_tx_cmd_cntl; 302 u32 sdio_tx_data_cntl1; 303 u32 sdio_tx_data_cntl2; 304 u32 sdio_rx_cmd_data_cntl1; 305 306 /* 0x2e0 */ 307 u32 sdio_rx_cmd_data_cntl2; 308 u32 sdcard_tx_cmd_cntl; 309 u32 sdcard_tx_data_cntl1; 310 u32 sdcard_tx_data_cntl2; 311 312 /* 0x2f0 */ 313 u32 sdcard_rx_cmd_data_cntl1; 314 u32 sdcard_rx_strobe_cntl; 315 u32 sdcard_rx_cmd_data_cntl2; 316 u32 emmc_tx_cmd_cntl; 317 318 /* 0x300 */ 319 u32 emmc_tx_data_cntl1; 320 u32 emmc_tx_data_cntl2; 321 u32 emmc_rx_cmd_data_cntl1; 322 u32 emmc_rx_strobe_cntl; 323 324 /* 0x310 */ 325 u32 emmc_rx_cmd_data_cntl2; 326 u32 emmc_master_sw_cntl; 327 u8 pcie_rp_selectable_deemphasis[6]; 328 u8 monitor_mwait_enable; 329 u8 hd_audio_dsp_uaa_compliance; 330 331 /* 0x320 */ 332 u32 ipc[4]; 333 334 /* 0x330 */ 335 u8 sata_ports_disable_dynamic_pg[2]; 336 u8 init_s3_cpu; 337 u8 skip_punit_init; 338 u8 unused_upd_space7[4]; 339 u8 port_usb20_per_port_tx_pe_half[8]; 340 341 /* 0x340 */ 342 u8 port_usb20_per_port_pe_txi_set[8]; 343 u8 port_usb20_per_port_txi_set[8]; 344 345 /* 0x350 */ 346 u8 port_usb20_hs_skew_sel[8]; 347 u8 port_usb20_i_usb_tx_emphasis_en[8]; 348 349 /* 0x360 */ 350 u8 port_usb20_per_port_rxi_set[8]; 351 u8 port_usb20_hs_npre_drv_sel[8]; 352 353 /* 0x370 */ 354 u8 os_selection; 355 u8 dptf_enabled; 356 u8 pwm_enabled; 357 u8 reserved_fsps_upd[13]; 358}; 359 360/** struct fsps_upd - FSP-S Configuration */ 361struct __packed fsps_upd { 362 struct fsp_upd_header header; 363 struct fsp_s_config config; 364 u8 unused_upd_space2[46]; 365 u16 upd_terminator; 366}; 367#endif 368 369#define PROC_TRACE_MEM_SIZE_DISABLE 0xff 370 371#define BOOT_P_STATE_HFM 0 372#define BOOT_P_STATE_LFM 1 373 374#define PKG_C_STATE_LIMIT_C0_C1 0 375#define PKG_C_STATE_LIMIT_C2 1 376#define PKG_C_STATE_LIMIT_C3 2 377#define PKG_C_STATE_LIMIT_C6 3 378#define PKG_C_STATE_LIMIT_C7 4 379#define PKG_C_STATE_LIMIT_C7S 5 380#define PKG_C_STATE_LIMIT_C8 6 381#define PKG_C_STATE_LIMIT_C9 7 382#define PKG_C_STATE_LIMIT_C10 8 383#define PKG_C_STATE_LIMIT_CMAX 9 384#define PKG_C_STATE_LIMIT_CPU_DEFAULT 254 385#define PKG_C_STATE_LIMIT_AUTO 255 386 387#define C_STATE_AUTO_DEMOTION_DISABLE_C1_C3 0 388#define C_STATE_AUTO_DEMOTION_ENABLE_C3_C6_C7_TO_C1 1 389#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C3 2 390#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C1_C3 3 391 392#define C_STATE_UN_DEMOTION_DISABLE_C1_C3 0 393#define C_STATE_UN_DEMOTION_ENABLE_C1 1 394#define C_STATE_UN_DEMOTION_ENABLE_C3 2 395#define C_STATE_UN_DEMOTION_ENABLE_C1_C3 3 396 397#define MAX_CORE_C_STATE_UNLIMITED 0 398#define MAX_CORE_C_STATE_C1 1 399#define MAX_CORE_C_STATE_C3 2 400#define MAX_CORE_C_STATE_C6 3 401#define MAX_CORE_C_STATE_C7 4 402#define MAX_CORE_C_STATE_C8 5 403#define MAX_CORE_C_STATE_C9 6 404#define MAX_CORE_C_STATE_C10 7 405#define MAX_CORE_C_STATE_CCX 8 406 407#define IPU_ACPI_MODE_DISABLE 0 408#define IPU_ACPI_MODE_IGFX_CHILD_DEVICE 1 409#define IPU_ACPI_MODE_ACPI_DEVICE 1 410 411#define CD_CLOCK_FREQ_144MHZ 0 412#define CD_CLOCK_FREQ_288MHZ 1 413#define CD_CLOCK_FREQ_384MHZ 2 414#define CD_CLOCK_FREQ_576MHZ 3 415#define CD_CLOCK_FREQ_624MHZ 4 416 417#define HDA_IO_BUFFER_OWNERSHIP_HDA_ALL_IO 0 418#define HDA_IO_BUFFER_OWNERSHIP_HDA_I2S_SPLIT 1 419#define HDA_IO_BUFFER_OWNERSHIP_I2S_ALL_IO 2 420 421#define HDA_IO_BUFFER_VOLTAGE_3V3 0 422#define HDA_IO_BUFFER_VOLTAGE_1V8 1 423 424#define HDA_VC_TYPE_VC0 0 425#define HDA_VC_TYPE_VC1 1 426 427#define HDA_LINK_FREQ_6MHZ 0 428#define HDA_LINK_FREQ_12MHZ 1 429#define HDA_LINK_FREQ_24MHZ 2 430#define HDA_LINK_FREQ_48MHZ 3 431#define HDA_LINK_FREQ_96MHZ 4 432#define HDA_LINK_FREQ_INVALID 5 433 434#define HDA_I_DISP_LINK_FREQ_6MHZ 0 435#define HDA_I_DISP_LINK_FREQ_12MHZ 1 436#define HDA_I_DISP_LINK_FREQ_24MHZ 2 437#define HDA_I_DISP_LINK_FREQ_48MHZ 3 438#define HDA_I_DISP_LINK_FREQ_96MHZ 4 439#define HDA_I_DISP_LINK_FREQ_INVALID 5 440 441#define HDA_I_DISP_LINK_T_MODE_2T 0 442#define HDA_I_DISP_LINK_T_MODE_1T 1 443 444#define HDA_DISP_DMIC_DISABLE 0 445#define HDA_DISP_DMIC_2CH_ARRAY 1 446#define HDA_DISP_DMIC_4CH_ARRAY 2 447 448#define HDA_CSE_MEM_TRANSFERS_VC0 0 449#define HDA_CSE_MEM_TRANSFERS_VC2 1 450 451#define HDA_HOST_MEM_TRANSFERS_VC0 0 452#define HDA_HOST_MEM_TRANSFERS_VC2 1 453 454#define HDA_DSP_FEATURE_MASK_WOV 0x1 455#define HDA_DSP_FEATURE_MASK_BT_SIDEBAND 0x2 456#define HDA_DSP_FEATURE_MASK_CODEC_VAD 0x4 457#define HDA_DSP_FEATURE_MASK_BT_INTEL_HFP 0x20 458#define HDA_DSP_FEATURE_MASK_BT_INTEL_A2DP 0x40 459#define HDA_DSP_FEATURE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80 460 461#define HDA_DSP_PP_MODULE_MASK_WOV 0x1 462#define HDA_DSP_PP_MODULE_MASK_BT_SIDEBAND 0x2 463#define HDA_DSP_PP_MODULE_MASK_CODEC_VAD 0x4 464#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_HFP 0x20 465#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_A2DP 0x40 466#define HDA_DSP_PP_MODULE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80 467 468#define I2CX_ENABLE_DISABLED 0 469#define I2CX_ENABLE_PCI_MODE 1 470#define I2CX_ENABLE_ACPI_MODE 2 471 472#define HSUARTX_ENABLE_DISABLED 0 473#define HSUARTX_ENABLE_PCI_MODE 1 474#define HSUARTX_ENABLE_ACPI_MODE 2 475 476#define SPIX_ENABLE_DISABLED 0 477#define SPIX_ENABLE_PCI_MODE 1 478#define SPIX_ENABLE_ACPI_MODE 2 479 480#define PCIE_RP_SPEED_AUTO 0 481#define PCIE_RP_SPEED_GEN1 1 482#define PCIE_RP_SPEED_GEN2 2 483#define PCIE_RP_SPEED_GEN3 3 484 485#define PCIE_RP_ASPM_DISABLE 0 486#define PCIE_RP_ASPM_L0S 1 487#define PCIE_RP_ASPM_L1 2 488#define PCIE_RP_ASPM_L0S_L1 3 489#define PCIE_RP_ASPM_AUTO 4 490 491#define PCIE_RP_L1_SUBSTATES_DISABLE 0 492#define PCIE_RP_L1_SUBSTATES_L1_1 1 493#define PCIE_RP_L1_SUBSTATES_L1_2 2 494#define PCIE_RP_L1_SUBSTATES_L1_1_L1_2 3 495 496#define SATA_MODE_AHCI 0 497#define SATA_MODE_RAID 1 498 499#define SATA_SPEED_LIMIT_SC_SATA_SPEED 0 500#define SATA_SPEED_LIMIT_1_5GBS 1 501#define SATA_SPEED_LIMIT_3GBS 2 502#define SATA_SPEED_LIMIT_6GBS 3 503 504#define SATA_PORT_SOLID_STATE_DRIVE_HARD_DISK_DRIVE 0 505#define SATA_PORT_SOLID_STATE_DRIVE_SOLID_STATE_DRIVE 1 506 507#define CRID_SETTING_DISABLE 0 508#define CRID_SETTING_CRID_1 1 509#define CRID_SETTING_CRID_2 2 510#define CRID_SETTING_CRID_3 3 511 512#define RESET_SELECT_WARM_RESET 0x6 513#define RESET_SELECT_COLD_RESET 0xe 514 515#define EMMC_HOST_SPEED_MAX_HS400 0 516#define EMMC_HOST_SPEED_MAX_HS200 1 517#define EMMC_HOST_SPEED_MAX_DDR50 2 518 519#define SERIAL_IRQ_MODE_QUIET_MODE 0 520#define SERIAL_IRQ_MODE_CONTINUOUS_MODE 1 521 522#define START_FRAME_PULSE_WIDTH_SCSFPW4CLK 0 523#define START_FRAME_PULSE_WIDTH_SCSFPW6CLK 1 524#define START_FRAME_PULSE_WIDTH_SCSFPW8CLK 1 525 526#define USB30_MODE_DISABLE 0 527#define USB30_MODE_ENABLE 1 528#define USB30_MODE_AUTO 2 529 530#define USB_OTG_DISABLE 0 531#define USB_OTG_PCI_MODE 1 532#define USB_OTG_ACPI_MODE 2 533 534#define SSIC_RATE_A_SERIES 1 535#define SSIC_RATE_B_SERIES 2 536 537#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0 538#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1 539#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2 540 541#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0 542#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1 543#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2 544#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3 545#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4 546#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5 547 548#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0 549#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1 550#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2 551 552#define PWR_BTN_OVERRIDE_PERIOD_4S 0 553#define PWR_BTN_OVERRIDE_PERIOD_6S 1 554#define PWR_BTN_OVERRIDE_PERIOD_8S 2 555#define PWR_BTN_OVERRIDE_PERIOD_10S 3 556#define PWR_BTN_OVERRIDE_PERIOD_12S 4 557#define PWR_BTN_OVERRIDE_PERIOD_14S 5 558 559#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0 560#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1 561#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2 562#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3 563#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4 564#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5 565 566#define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0 567#define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1 568 569#define OS_SELECTION_WINDOWS 0 570#define OS_SELECTION_ANDROID 1 571#define OS_SELECTION_LINUX 3 572 573#endif 574