1296177Sjhibbits/* SPDX-License-Identifier: GPL-2.0+ */ 2296177Sjhibbits/* 3296177Sjhibbits * Copyright (C) 2022 StarFive Technology Co., Ltd. 4296177Sjhibbits * 5296177Sjhibbits * Author: Yanhong Wang <yanhong.wang@starfivetech.com> 6296177Sjhibbits */ 7296177Sjhibbits 8296177Sjhibbits#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ 9296177Sjhibbits#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ 10296177Sjhibbits 11296177Sjhibbits#define JH7110_SYSCLK_PLL0_OUT 0 12296177Sjhibbits#define JH7110_SYSCLK_PLL1_OUT 1 13296177Sjhibbits#define JH7110_SYSCLK_PLL2_OUT 2 14296177Sjhibbits#define JH7110_PLLCLK_END 3 15296177Sjhibbits 16296177Sjhibbits#define JH7110_SYSCLK_CPU_ROOT 0 17296177Sjhibbits#define JH7110_SYSCLK_CPU_CORE 1 18296177Sjhibbits#define JH7110_SYSCLK_CPU_BUS 2 19296177Sjhibbits#define JH7110_SYSCLK_GPU_ROOT 3 20296177Sjhibbits#define JH7110_SYSCLK_PERH_ROOT 4 21296177Sjhibbits#define JH7110_SYSCLK_BUS_ROOT 5 22296177Sjhibbits#define JH7110_SYSCLK_NOCSTG_BUS 6 23296177Sjhibbits#define JH7110_SYSCLK_AXI_CFG0 7 24296177Sjhibbits#define JH7110_SYSCLK_STG_AXIAHB 8 25296177Sjhibbits#define JH7110_SYSCLK_AHB0 9 26296177Sjhibbits#define JH7110_SYSCLK_AHB1 10 27296177Sjhibbits#define JH7110_SYSCLK_APB_BUS 11 28296177Sjhibbits#define JH7110_SYSCLK_APB0 12 29296177Sjhibbits#define JH7110_SYSCLK_PLL0_DIV2 13 30296177Sjhibbits#define JH7110_SYSCLK_PLL1_DIV2 14 31296177Sjhibbits#define JH7110_SYSCLK_PLL2_DIV2 15 32296177Sjhibbits#define JH7110_SYSCLK_AUDIO_ROOT 16 33296177Sjhibbits#define JH7110_SYSCLK_MCLK_INNER 17 34296177Sjhibbits#define JH7110_SYSCLK_MCLK 18 35296177Sjhibbits#define JH7110_SYSCLK_MCLK_OUT 19 36296177Sjhibbits#define JH7110_SYSCLK_ISP_2X 20 37296177Sjhibbits#define JH7110_SYSCLK_ISP_AXI 21 38296177Sjhibbits#define JH7110_SYSCLK_GCLK0 22 39296177Sjhibbits#define JH7110_SYSCLK_GCLK1 23 40296177Sjhibbits#define JH7110_SYSCLK_GCLK2 24 41296177Sjhibbits#define JH7110_SYSCLK_CORE 25 42296177Sjhibbits#define JH7110_SYSCLK_CORE1 26 43296177Sjhibbits#define JH7110_SYSCLK_CORE2 27 44296177Sjhibbits#define JH7110_SYSCLK_CORE3 28 45296177Sjhibbits#define JH7110_SYSCLK_CORE4 29 46296177Sjhibbits#define JH7110_SYSCLK_DEBUG 30 47296177Sjhibbits#define JH7110_SYSCLK_RTC_TOGGLE 31 48296177Sjhibbits#define JH7110_SYSCLK_TRACE0 32 49296177Sjhibbits#define JH7110_SYSCLK_TRACE1 33 50296177Sjhibbits#define JH7110_SYSCLK_TRACE2 34 51296177Sjhibbits#define JH7110_SYSCLK_TRACE3 35 52296177Sjhibbits#define JH7110_SYSCLK_TRACE4 36 53296177Sjhibbits#define JH7110_SYSCLK_TRACE_COM 37 54296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 55296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 56296177Sjhibbits#define JH7110_SYSCLK_OSC_DIV2 40 57296177Sjhibbits#define JH7110_SYSCLK_PLL1_DIV4 41 58296177Sjhibbits#define JH7110_SYSCLK_PLL1_DIV8 42 59296177Sjhibbits#define JH7110_SYSCLK_DDR_BUS 43 60296177Sjhibbits#define JH7110_SYSCLK_DDR_AXI 44 61296177Sjhibbits#define JH7110_SYSCLK_GPU_CORE 45 62296177Sjhibbits#define JH7110_SYSCLK_GPU_CORE_CLK 46 63296177Sjhibbits#define JH7110_SYSCLK_GPU_SYS_CLK 47 64296177Sjhibbits#define JH7110_SYSCLK_GPU_APB 48 65296177Sjhibbits#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 66296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 67296177Sjhibbits#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 68296177Sjhibbits#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 69296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 70296177Sjhibbits#define JH7110_SYSCLK_HIFI4_CORE 54 71296177Sjhibbits#define JH7110_SYSCLK_HIFI4_AXI 55 72296177Sjhibbits#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 73296177Sjhibbits#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 74296177Sjhibbits#define JH7110_SYSCLK_VOUT_SRC 58 75296177Sjhibbits#define JH7110_SYSCLK_VOUT_AXI 59 76296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 77296177Sjhibbits#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 78296177Sjhibbits#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 79296177Sjhibbits#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 80296177Sjhibbits#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 81296177Sjhibbits#define JH7110_SYSCLK_JPEGC_AXI 65 82296177Sjhibbits#define JH7110_SYSCLK_CODAJ12_AXI 66 83296177Sjhibbits#define JH7110_SYSCLK_CODAJ12_CORE 67 84296177Sjhibbits#define JH7110_SYSCLK_CODAJ12_APB 68 85296177Sjhibbits#define JH7110_SYSCLK_VDEC_AXI 69 86296177Sjhibbits#define JH7110_SYSCLK_WAVE511_AXI 70 87296177Sjhibbits#define JH7110_SYSCLK_WAVE511_BPU 71 88296177Sjhibbits#define JH7110_SYSCLK_WAVE511_VCE 72 89296177Sjhibbits#define JH7110_SYSCLK_WAVE511_APB 73 90296177Sjhibbits#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 91296177Sjhibbits#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 92296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 93296177Sjhibbits#define JH7110_SYSCLK_VENC_AXI 77 94296177Sjhibbits#define JH7110_SYSCLK_WAVE420L_AXI 78 95296177Sjhibbits#define JH7110_SYSCLK_WAVE420L_BPU 79 96296177Sjhibbits#define JH7110_SYSCLK_WAVE420L_VCE 80 97296177Sjhibbits#define JH7110_SYSCLK_WAVE420L_APB 81 98296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 99296177Sjhibbits#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 100296177Sjhibbits#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 101296177Sjhibbits#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 102296177Sjhibbits#define JH7110_SYSCLK_AXIMEM2_AXI 86 103296177Sjhibbits#define JH7110_SYSCLK_QSPI_AHB 87 104296177Sjhibbits#define JH7110_SYSCLK_QSPI_APB 88 105296177Sjhibbits#define JH7110_SYSCLK_QSPI_REF_SRC 89 106296177Sjhibbits#define JH7110_SYSCLK_QSPI_REF 90 107296177Sjhibbits#define JH7110_SYSCLK_SDIO0_AHB 91 108296177Sjhibbits#define JH7110_SYSCLK_SDIO1_AHB 92 109296177Sjhibbits#define JH7110_SYSCLK_SDIO0_SDCARD 93 110296177Sjhibbits#define JH7110_SYSCLK_SDIO1_SDCARD 94 111296177Sjhibbits#define JH7110_SYSCLK_USB_125M 95 112296177Sjhibbits#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 113296177Sjhibbits#define JH7110_SYSCLK_GMAC1_AHB 97 114296177Sjhibbits#define JH7110_SYSCLK_GMAC1_AXI 98 115296177Sjhibbits#define JH7110_SYSCLK_GMAC_SRC 99 116296177Sjhibbits#define JH7110_SYSCLK_GMAC1_GTXCLK 100 117296177Sjhibbits#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 118296177Sjhibbits#define JH7110_SYSCLK_GMAC1_PTP 102 119296177Sjhibbits#define JH7110_SYSCLK_GMAC1_RX 103 120296177Sjhibbits#define JH7110_SYSCLK_GMAC1_RX_INV 104 121296177Sjhibbits#define JH7110_SYSCLK_GMAC1_TX 105 122296177Sjhibbits#define JH7110_SYSCLK_GMAC1_TX_INV 106 123296177Sjhibbits#define JH7110_SYSCLK_GMAC1_GTXC 107 124296177Sjhibbits#define JH7110_SYSCLK_GMAC0_GTXCLK 108 125296177Sjhibbits#define JH7110_SYSCLK_GMAC0_PTP 109 126296177Sjhibbits#define JH7110_SYSCLK_GMAC_PHY 110 127296177Sjhibbits#define JH7110_SYSCLK_GMAC0_GTXC 111 128296177Sjhibbits#define JH7110_SYSCLK_IOMUX_APB 112 129296177Sjhibbits#define JH7110_SYSCLK_MAILBOX 113 130296177Sjhibbits#define JH7110_SYSCLK_INT_CTRL_APB 114 131296177Sjhibbits#define JH7110_SYSCLK_CAN0_APB 115 132296177Sjhibbits#define JH7110_SYSCLK_CAN0_TIMER 116 133296177Sjhibbits#define JH7110_SYSCLK_CAN0_CAN 117 134296177Sjhibbits#define JH7110_SYSCLK_CAN1_APB 118 135296177Sjhibbits#define JH7110_SYSCLK_CAN1_TIMER 119 136296177Sjhibbits#define JH7110_SYSCLK_CAN1_CAN 120 137296177Sjhibbits#define JH7110_SYSCLK_PWM_APB 121 138296177Sjhibbits#define JH7110_SYSCLK_WDT_APB 122 139296177Sjhibbits#define JH7110_SYSCLK_WDT_CORE 123 140296177Sjhibbits#define JH7110_SYSCLK_TIMER_APB 124 141296177Sjhibbits#define JH7110_SYSCLK_TIMER0 125 142296177Sjhibbits#define JH7110_SYSCLK_TIMER1 126 143296177Sjhibbits#define JH7110_SYSCLK_TIMER2 127 144296177Sjhibbits#define JH7110_SYSCLK_TIMER3 128 145296177Sjhibbits#define JH7110_SYSCLK_TEMP_APB 129 146296177Sjhibbits#define JH7110_SYSCLK_TEMP_CORE 130 147296177Sjhibbits#define JH7110_SYSCLK_SPI0_APB 131 148296177Sjhibbits#define JH7110_SYSCLK_SPI1_APB 132 149296177Sjhibbits#define JH7110_SYSCLK_SPI2_APB 133 150296177Sjhibbits#define JH7110_SYSCLK_SPI3_APB 134 151296177Sjhibbits#define JH7110_SYSCLK_SPI4_APB 135 152296177Sjhibbits#define JH7110_SYSCLK_SPI5_APB 136 153296177Sjhibbits#define JH7110_SYSCLK_SPI6_APB 137 154296177Sjhibbits#define JH7110_SYSCLK_I2C0_APB 138 155296177Sjhibbits#define JH7110_SYSCLK_I2C1_APB 139 156296177Sjhibbits#define JH7110_SYSCLK_I2C2_APB 140 157296177Sjhibbits#define JH7110_SYSCLK_I2C3_APB 141 158296177Sjhibbits#define JH7110_SYSCLK_I2C4_APB 142 159296177Sjhibbits#define JH7110_SYSCLK_I2C5_APB 143 160296177Sjhibbits#define JH7110_SYSCLK_I2C6_APB 144 161296177Sjhibbits#define JH7110_SYSCLK_UART0_APB 145 162296177Sjhibbits#define JH7110_SYSCLK_UART0_CORE 146 163296177Sjhibbits#define JH7110_SYSCLK_UART1_APB 147 164296177Sjhibbits#define JH7110_SYSCLK_UART1_CORE 148 165296177Sjhibbits#define JH7110_SYSCLK_UART2_APB 149 166296177Sjhibbits#define JH7110_SYSCLK_UART2_CORE 150 167296177Sjhibbits#define JH7110_SYSCLK_UART3_APB 151 168296177Sjhibbits#define JH7110_SYSCLK_UART3_CORE 152 169296177Sjhibbits#define JH7110_SYSCLK_UART4_APB 153 170296177Sjhibbits#define JH7110_SYSCLK_UART4_CORE 154 171296177Sjhibbits#define JH7110_SYSCLK_UART5_APB 155 172296177Sjhibbits#define JH7110_SYSCLK_UART5_CORE 156 173296177Sjhibbits#define JH7110_SYSCLK_PWMDAC_APB 157 174296177Sjhibbits#define JH7110_SYSCLK_PWMDAC_CORE 158 175296177Sjhibbits#define JH7110_SYSCLK_SPDIF_APB 159 176296177Sjhibbits#define JH7110_SYSCLK_SPDIF_CORE 160 177296177Sjhibbits#define JH7110_SYSCLK_I2STX0_APB 161 178296177Sjhibbits#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 179296177Sjhibbits#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 180296177Sjhibbits#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 181296177Sjhibbits#define JH7110_SYSCLK_I2STX0_BCLK 165 182296177Sjhibbits#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 183296177Sjhibbits#define JH7110_SYSCLK_I2STX0_LRCK 167 184296177Sjhibbits#define JH7110_SYSCLK_I2STX1_APB 168 185296177Sjhibbits#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 186296177Sjhibbits#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 187296177Sjhibbits#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 188296177Sjhibbits#define JH7110_SYSCLK_I2STX1_BCLK 172 189296177Sjhibbits#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 190296177Sjhibbits#define JH7110_SYSCLK_I2STX1_LRCK 174 191296177Sjhibbits#define JH7110_SYSCLK_I2SRX_APB 175 192296177Sjhibbits#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 193296177Sjhibbits#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 194296177Sjhibbits#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 195296177Sjhibbits#define JH7110_SYSCLK_I2SRX_BCLK 179 196296177Sjhibbits#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 197296177Sjhibbits#define JH7110_SYSCLK_I2SRX_LRCK 181 198296177Sjhibbits#define JH7110_SYSCLK_PDM_DMIC 182 199296177Sjhibbits#define JH7110_SYSCLK_PDM_APB 183 200296177Sjhibbits#define JH7110_SYSCLK_TDM_AHB 184 201296177Sjhibbits#define JH7110_SYSCLK_TDM_APB 185 202296177Sjhibbits#define JH7110_SYSCLK_TDM_INTERNAL 186 203296177Sjhibbits#define JH7110_SYSCLK_TDM_CLK_TDM 187 204296177Sjhibbits#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 205296177Sjhibbits#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 206296177Sjhibbits 207296177Sjhibbits#define JH7110_SYSCLK_END 190 208296177Sjhibbits 209296177Sjhibbits#define JH7110_AONCLK_OSC_DIV4 0 210296177Sjhibbits#define JH7110_AONCLK_APB_FUNC 1 211296177Sjhibbits#define JH7110_AONCLK_GMAC0_AHB 2 212296177Sjhibbits#define JH7110_AONCLK_GMAC0_AXI 3 213296177Sjhibbits#define JH7110_AONCLK_GMAC0_RMII_RTX 4 214296177Sjhibbits#define JH7110_AONCLK_GMAC0_TX 5 215296177Sjhibbits#define JH7110_AONCLK_GMAC0_TX_INV 6 216296177Sjhibbits#define JH7110_AONCLK_GMAC0_RX 7 217296177Sjhibbits#define JH7110_AONCLK_GMAC0_RX_INV 8 218296177Sjhibbits#define JH7110_AONCLK_OTPC_APB 9 219296177Sjhibbits#define JH7110_AONCLK_RTC_APB 10 220296177Sjhibbits#define JH7110_AONCLK_RTC_INTERNAL 11 221296177Sjhibbits#define JH7110_AONCLK_RTC_32K 12 222296177Sjhibbits#define JH7110_AONCLK_RTC_CAL 13 223296177Sjhibbits 224296177Sjhibbits#define JH7110_AONCLK_END 14 225296177Sjhibbits 226296177Sjhibbits#define JH7110_STGCLK_HIFI4_CORE 0 227296177Sjhibbits#define JH7110_STGCLK_USB_APB 1 228296177Sjhibbits#define JH7110_STGCLK_USB_UTMI_APB 2 229296177Sjhibbits#define JH7110_STGCLK_USB_AXI 3 230296177Sjhibbits#define JH7110_STGCLK_USB_LPM 4 231296177Sjhibbits#define JH7110_STGCLK_USB_STB 5 232296177Sjhibbits#define JH7110_STGCLK_USB_APP_125 6 233296177Sjhibbits#define JH7110_STGCLK_USB_REFCLK 7 234296177Sjhibbits#define JH7110_STGCLK_PCIE0_AXI 8 235296177Sjhibbits#define JH7110_STGCLK_PCIE0_APB 9 236296177Sjhibbits#define JH7110_STGCLK_PCIE0_TL 10 237296177Sjhibbits#define JH7110_STGCLK_PCIE1_AXI 11 238296177Sjhibbits#define JH7110_STGCLK_PCIE1_APB 12 239296177Sjhibbits#define JH7110_STGCLK_PCIE1_TL 13 240296177Sjhibbits#define JH7110_STGCLK_PCIE01_MAIN 14 241296177Sjhibbits#define JH7110_STGCLK_SEC_HCLK 15 242296177Sjhibbits#define JH7110_STGCLK_SEC_MISCAHB 16 243296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 244296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP0_BUS 18 245296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP0_STG 19 246296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 247296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP1_BUS 21 248296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP1_STG 22 249296177Sjhibbits#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 250296177Sjhibbits#define JH7110_STGCLK_E2_RTC 24 251296177Sjhibbits#define JH7110_STGCLK_E2_CORE 25 252296177Sjhibbits#define JH7110_STGCLK_E2_DBG 26 253296177Sjhibbits#define JH7110_STGCLK_DMA1P_AXI 27 254296177Sjhibbits#define JH7110_STGCLK_DMA1P_AHB 28 255296177Sjhibbits 256296177Sjhibbits#define JH7110_STGCLK_END 29 257296177Sjhibbits 258296177Sjhibbits#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ 259296177Sjhibbits