1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * 5 * Author: Yanhong Wang <yanhong.wang@starfivetech.com> 6 */ 7 8#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ 9#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ 10 11#define JH7110_SYSCLK_PLL0_OUT 0 12#define JH7110_SYSCLK_PLL1_OUT 1 13#define JH7110_SYSCLK_PLL2_OUT 2 14#define JH7110_PLLCLK_END 3 15 16#define JH7110_SYSCLK_CPU_ROOT 0 17#define JH7110_SYSCLK_CPU_CORE 1 18#define JH7110_SYSCLK_CPU_BUS 2 19#define JH7110_SYSCLK_GPU_ROOT 3 20#define JH7110_SYSCLK_PERH_ROOT 4 21#define JH7110_SYSCLK_BUS_ROOT 5 22#define JH7110_SYSCLK_NOCSTG_BUS 6 23#define JH7110_SYSCLK_AXI_CFG0 7 24#define JH7110_SYSCLK_STG_AXIAHB 8 25#define JH7110_SYSCLK_AHB0 9 26#define JH7110_SYSCLK_AHB1 10 27#define JH7110_SYSCLK_APB_BUS 11 28#define JH7110_SYSCLK_APB0 12 29#define JH7110_SYSCLK_PLL0_DIV2 13 30#define JH7110_SYSCLK_PLL1_DIV2 14 31#define JH7110_SYSCLK_PLL2_DIV2 15 32#define JH7110_SYSCLK_AUDIO_ROOT 16 33#define JH7110_SYSCLK_MCLK_INNER 17 34#define JH7110_SYSCLK_MCLK 18 35#define JH7110_SYSCLK_MCLK_OUT 19 36#define JH7110_SYSCLK_ISP_2X 20 37#define JH7110_SYSCLK_ISP_AXI 21 38#define JH7110_SYSCLK_GCLK0 22 39#define JH7110_SYSCLK_GCLK1 23 40#define JH7110_SYSCLK_GCLK2 24 41#define JH7110_SYSCLK_CORE 25 42#define JH7110_SYSCLK_CORE1 26 43#define JH7110_SYSCLK_CORE2 27 44#define JH7110_SYSCLK_CORE3 28 45#define JH7110_SYSCLK_CORE4 29 46#define JH7110_SYSCLK_DEBUG 30 47#define JH7110_SYSCLK_RTC_TOGGLE 31 48#define JH7110_SYSCLK_TRACE0 32 49#define JH7110_SYSCLK_TRACE1 33 50#define JH7110_SYSCLK_TRACE2 34 51#define JH7110_SYSCLK_TRACE3 35 52#define JH7110_SYSCLK_TRACE4 36 53#define JH7110_SYSCLK_TRACE_COM 37 54#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 55#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 56#define JH7110_SYSCLK_OSC_DIV2 40 57#define JH7110_SYSCLK_PLL1_DIV4 41 58#define JH7110_SYSCLK_PLL1_DIV8 42 59#define JH7110_SYSCLK_DDR_BUS 43 60#define JH7110_SYSCLK_DDR_AXI 44 61#define JH7110_SYSCLK_GPU_CORE 45 62#define JH7110_SYSCLK_GPU_CORE_CLK 46 63#define JH7110_SYSCLK_GPU_SYS_CLK 47 64#define JH7110_SYSCLK_GPU_APB 48 65#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 66#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 67#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 68#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 69#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 70#define JH7110_SYSCLK_HIFI4_CORE 54 71#define JH7110_SYSCLK_HIFI4_AXI 55 72#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 73#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 74#define JH7110_SYSCLK_VOUT_SRC 58 75#define JH7110_SYSCLK_VOUT_AXI 59 76#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 77#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 78#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 79#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 80#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 81#define JH7110_SYSCLK_JPEGC_AXI 65 82#define JH7110_SYSCLK_CODAJ12_AXI 66 83#define JH7110_SYSCLK_CODAJ12_CORE 67 84#define JH7110_SYSCLK_CODAJ12_APB 68 85#define JH7110_SYSCLK_VDEC_AXI 69 86#define JH7110_SYSCLK_WAVE511_AXI 70 87#define JH7110_SYSCLK_WAVE511_BPU 71 88#define JH7110_SYSCLK_WAVE511_VCE 72 89#define JH7110_SYSCLK_WAVE511_APB 73 90#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 91#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 92#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 93#define JH7110_SYSCLK_VENC_AXI 77 94#define JH7110_SYSCLK_WAVE420L_AXI 78 95#define JH7110_SYSCLK_WAVE420L_BPU 79 96#define JH7110_SYSCLK_WAVE420L_VCE 80 97#define JH7110_SYSCLK_WAVE420L_APB 81 98#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 99#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 100#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 101#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 102#define JH7110_SYSCLK_AXIMEM2_AXI 86 103#define JH7110_SYSCLK_QSPI_AHB 87 104#define JH7110_SYSCLK_QSPI_APB 88 105#define JH7110_SYSCLK_QSPI_REF_SRC 89 106#define JH7110_SYSCLK_QSPI_REF 90 107#define JH7110_SYSCLK_SDIO0_AHB 91 108#define JH7110_SYSCLK_SDIO1_AHB 92 109#define JH7110_SYSCLK_SDIO0_SDCARD 93 110#define JH7110_SYSCLK_SDIO1_SDCARD 94 111#define JH7110_SYSCLK_USB_125M 95 112#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 113#define JH7110_SYSCLK_GMAC1_AHB 97 114#define JH7110_SYSCLK_GMAC1_AXI 98 115#define JH7110_SYSCLK_GMAC_SRC 99 116#define JH7110_SYSCLK_GMAC1_GTXCLK 100 117#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 118#define JH7110_SYSCLK_GMAC1_PTP 102 119#define JH7110_SYSCLK_GMAC1_RX 103 120#define JH7110_SYSCLK_GMAC1_RX_INV 104 121#define JH7110_SYSCLK_GMAC1_TX 105 122#define JH7110_SYSCLK_GMAC1_TX_INV 106 123#define JH7110_SYSCLK_GMAC1_GTXC 107 124#define JH7110_SYSCLK_GMAC0_GTXCLK 108 125#define JH7110_SYSCLK_GMAC0_PTP 109 126#define JH7110_SYSCLK_GMAC_PHY 110 127#define JH7110_SYSCLK_GMAC0_GTXC 111 128#define JH7110_SYSCLK_IOMUX_APB 112 129#define JH7110_SYSCLK_MAILBOX 113 130#define JH7110_SYSCLK_INT_CTRL_APB 114 131#define JH7110_SYSCLK_CAN0_APB 115 132#define JH7110_SYSCLK_CAN0_TIMER 116 133#define JH7110_SYSCLK_CAN0_CAN 117 134#define JH7110_SYSCLK_CAN1_APB 118 135#define JH7110_SYSCLK_CAN1_TIMER 119 136#define JH7110_SYSCLK_CAN1_CAN 120 137#define JH7110_SYSCLK_PWM_APB 121 138#define JH7110_SYSCLK_WDT_APB 122 139#define JH7110_SYSCLK_WDT_CORE 123 140#define JH7110_SYSCLK_TIMER_APB 124 141#define JH7110_SYSCLK_TIMER0 125 142#define JH7110_SYSCLK_TIMER1 126 143#define JH7110_SYSCLK_TIMER2 127 144#define JH7110_SYSCLK_TIMER3 128 145#define JH7110_SYSCLK_TEMP_APB 129 146#define JH7110_SYSCLK_TEMP_CORE 130 147#define JH7110_SYSCLK_SPI0_APB 131 148#define JH7110_SYSCLK_SPI1_APB 132 149#define JH7110_SYSCLK_SPI2_APB 133 150#define JH7110_SYSCLK_SPI3_APB 134 151#define JH7110_SYSCLK_SPI4_APB 135 152#define JH7110_SYSCLK_SPI5_APB 136 153#define JH7110_SYSCLK_SPI6_APB 137 154#define JH7110_SYSCLK_I2C0_APB 138 155#define JH7110_SYSCLK_I2C1_APB 139 156#define JH7110_SYSCLK_I2C2_APB 140 157#define JH7110_SYSCLK_I2C3_APB 141 158#define JH7110_SYSCLK_I2C4_APB 142 159#define JH7110_SYSCLK_I2C5_APB 143 160#define JH7110_SYSCLK_I2C6_APB 144 161#define JH7110_SYSCLK_UART0_APB 145 162#define JH7110_SYSCLK_UART0_CORE 146 163#define JH7110_SYSCLK_UART1_APB 147 164#define JH7110_SYSCLK_UART1_CORE 148 165#define JH7110_SYSCLK_UART2_APB 149 166#define JH7110_SYSCLK_UART2_CORE 150 167#define JH7110_SYSCLK_UART3_APB 151 168#define JH7110_SYSCLK_UART3_CORE 152 169#define JH7110_SYSCLK_UART4_APB 153 170#define JH7110_SYSCLK_UART4_CORE 154 171#define JH7110_SYSCLK_UART5_APB 155 172#define JH7110_SYSCLK_UART5_CORE 156 173#define JH7110_SYSCLK_PWMDAC_APB 157 174#define JH7110_SYSCLK_PWMDAC_CORE 158 175#define JH7110_SYSCLK_SPDIF_APB 159 176#define JH7110_SYSCLK_SPDIF_CORE 160 177#define JH7110_SYSCLK_I2STX0_APB 161 178#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 179#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 180#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 181#define JH7110_SYSCLK_I2STX0_BCLK 165 182#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 183#define JH7110_SYSCLK_I2STX0_LRCK 167 184#define JH7110_SYSCLK_I2STX1_APB 168 185#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 186#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 187#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 188#define JH7110_SYSCLK_I2STX1_BCLK 172 189#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 190#define JH7110_SYSCLK_I2STX1_LRCK 174 191#define JH7110_SYSCLK_I2SRX_APB 175 192#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 193#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 194#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 195#define JH7110_SYSCLK_I2SRX_BCLK 179 196#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 197#define JH7110_SYSCLK_I2SRX_LRCK 181 198#define JH7110_SYSCLK_PDM_DMIC 182 199#define JH7110_SYSCLK_PDM_APB 183 200#define JH7110_SYSCLK_TDM_AHB 184 201#define JH7110_SYSCLK_TDM_APB 185 202#define JH7110_SYSCLK_TDM_INTERNAL 186 203#define JH7110_SYSCLK_TDM_CLK_TDM 187 204#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 205#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 206 207#define JH7110_SYSCLK_END 190 208 209#define JH7110_AONCLK_OSC_DIV4 0 210#define JH7110_AONCLK_APB_FUNC 1 211#define JH7110_AONCLK_GMAC0_AHB 2 212#define JH7110_AONCLK_GMAC0_AXI 3 213#define JH7110_AONCLK_GMAC0_RMII_RTX 4 214#define JH7110_AONCLK_GMAC0_TX 5 215#define JH7110_AONCLK_GMAC0_TX_INV 6 216#define JH7110_AONCLK_GMAC0_RX 7 217#define JH7110_AONCLK_GMAC0_RX_INV 8 218#define JH7110_AONCLK_OTPC_APB 9 219#define JH7110_AONCLK_RTC_APB 10 220#define JH7110_AONCLK_RTC_INTERNAL 11 221#define JH7110_AONCLK_RTC_32K 12 222#define JH7110_AONCLK_RTC_CAL 13 223 224#define JH7110_AONCLK_END 14 225 226#define JH7110_STGCLK_HIFI4_CORE 0 227#define JH7110_STGCLK_USB_APB 1 228#define JH7110_STGCLK_USB_UTMI_APB 2 229#define JH7110_STGCLK_USB_AXI 3 230#define JH7110_STGCLK_USB_LPM 4 231#define JH7110_STGCLK_USB_STB 5 232#define JH7110_STGCLK_USB_APP_125 6 233#define JH7110_STGCLK_USB_REFCLK 7 234#define JH7110_STGCLK_PCIE0_AXI 8 235#define JH7110_STGCLK_PCIE0_APB 9 236#define JH7110_STGCLK_PCIE0_TL 10 237#define JH7110_STGCLK_PCIE1_AXI 11 238#define JH7110_STGCLK_PCIE1_APB 12 239#define JH7110_STGCLK_PCIE1_TL 13 240#define JH7110_STGCLK_PCIE01_MAIN 14 241#define JH7110_STGCLK_SEC_HCLK 15 242#define JH7110_STGCLK_SEC_MISCAHB 16 243#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 244#define JH7110_STGCLK_MTRX_GRP0_BUS 18 245#define JH7110_STGCLK_MTRX_GRP0_STG 19 246#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 247#define JH7110_STGCLK_MTRX_GRP1_BUS 21 248#define JH7110_STGCLK_MTRX_GRP1_STG 22 249#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 250#define JH7110_STGCLK_E2_RTC 24 251#define JH7110_STGCLK_E2_CORE 25 252#define JH7110_STGCLK_E2_DBG 26 253#define JH7110_STGCLK_DMA1P_AXI 27 254#define JH7110_STGCLK_DMA1P_AHB 28 255 256#define JH7110_STGCLK_END 29 257 258#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ 259