1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-router/intel-irq.h> 9 10/include/ "skeleton.dtsi" 11/include/ "serial.dtsi" 12/include/ "keyboard.dtsi" 13/include/ "reset.dtsi" 14/include/ "rtc.dtsi" 15 16#include "tsc_timer.dtsi" 17#include "smbios.dtsi" 18 19/ { 20 model = "Intel Cougar Canyon 2"; 21 compatible = "intel,cougarcanyon2", "intel,chiefriver"; 22 23 aliases { 24 spi0 = &spi0; 25 }; 26 27 config { 28 silent_console = <0>; 29 }; 30 31 chosen { 32 stdout-path = "/serial"; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 device_type = "cpu"; 41 compatible = "intel,core-gen3"; 42 reg = <0>; 43 intel,apic-id = <0>; 44 }; 45 46 cpu@1 { 47 device_type = "cpu"; 48 compatible = "intel,core-gen3"; 49 reg = <1>; 50 intel,apic-id = <1>; 51 }; 52 53 cpu@2 { 54 device_type = "cpu"; 55 compatible = "intel,core-gen3"; 56 reg = <2>; 57 intel,apic-id = <2>; 58 }; 59 60 cpu@3 { 61 device_type = "cpu"; 62 compatible = "intel,core-gen3"; 63 reg = <3>; 64 intel,apic-id = <3>; 65 }; 66 }; 67 68 microcode { 69 update@0 { 70#include "microcode/m12306a2_00000008.dtsi" 71 }; 72 update@1 { 73#include "microcode/m12306a4_00000007.dtsi" 74 }; 75 update@2 { 76#include "microcode/m12306a5_00000007.dtsi" 77 }; 78 update@3 { 79#include "microcode/m12306a8_00000010.dtsi" 80 }; 81 update@4 { 82#include "microcode/m12306a9_0000001b.dtsi" 83 }; 84 }; 85 86 fsp { 87 compatible = "intel,ivybridge-fsp"; 88 fsp,enable-ht; 89 }; 90 91 pci { 92 #address-cells = <3>; 93 #size-cells = <2>; 94 compatible = "pci-x86"; 95 bootph-all; 96 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 97 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 98 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 99 100 pch@1f,0 { 101 reg = <0x0000f800 0 0 0 0>; 102 compatible = "intel,bd82x6x"; 103 bootph-all; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 107 irq-router { 108 compatible = "intel,irq-router"; 109 intel,pirq-config = "pci"; 110 intel,actl-8bit; 111 intel,actl-addr = <0x44>; 112 intel,pirq-link = <0x60 8>; 113 intel,pirq-regmap = < 114 PIRQA 0 115 PIRQB 1 116 PIRQC 2 117 PIRQD 3 118 PIRQE 8 119 PIRQF 9 120 PIRQG 10 121 PIRQH 11 122 >; 123 intel,pirq-mask = <0xcee0>; 124 intel,pirq-routing = < 125 /* Panther Point PCI devices */ 126 PCI_BDF(0, 2, 0) INTA PIRQA 127 PCI_BDF(0, 20, 0) INTA PIRQA 128 PCI_BDF(0, 22, 0) INTA PIRQA 129 PCI_BDF(0, 22, 1) INTB PIRQB 130 PCI_BDF(0, 22, 2) INTC PIRQC 131 PCI_BDF(0, 22, 3) INTD PIRQD 132 PCI_BDF(0, 25, 0) INTA PIRQA 133 PCI_BDF(0, 26, 0) INTA PIRQA 134 PCI_BDF(0, 27, 0) INTB PIRQA 135 PCI_BDF(0, 28, 0) INTA PIRQA 136 PCI_BDF(0, 28, 1) INTB PIRQB 137 PCI_BDF(0, 28, 2) INTC PIRQC 138 PCI_BDF(0, 28, 3) INTD PIRQD 139 PCI_BDF(0, 28, 4) INTA PIRQA 140 PCI_BDF(0, 28, 5) INTB PIRQB 141 PCI_BDF(0, 28, 6) INTC PIRQC 142 PCI_BDF(0, 28, 7) INTD PIRQD 143 PCI_BDF(0, 29, 0) INTA PIRQA 144 PCI_BDF(0, 31, 2) INTB PIRQB 145 PCI_BDF(0, 31, 3) INTC PIRQC 146 PCI_BDF(0, 31, 5) INTB PIRQB 147 PCI_BDF(0, 31, 6) INTC PIRQC 148 >; 149 }; 150 151 spi0: spi { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 compatible = "intel,ich9-spi"; 155 intel,spi-lock-down; 156 157 spi-flash@0 { 158 reg = <0>; 159 m25p,fast-read; 160 compatible = "winbond,w25q64bv", "jedec,spi-nor"; 161 memory-map = <0xff800000 0x00800000>; 162 }; 163 }; 164 165 gpioa { 166 compatible = "intel,ich6-gpio"; 167 bootph-all; 168 reg = <0 0x10>; 169 bank-name = "A"; 170 }; 171 172 gpiob { 173 compatible = "intel,ich6-gpio"; 174 bootph-all; 175 reg = <0x30 0x10>; 176 bank-name = "B"; 177 }; 178 179 gpioc { 180 compatible = "intel,ich6-gpio"; 181 bootph-all; 182 reg = <0x40 0x10>; 183 bank-name = "C"; 184 }; 185 }; 186 }; 187 188}; 189