1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Google, Inc 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <errno.h> 9#include <fdtdec.h> 10#include <log.h> 11#include <pch.h> 12#include <pci.h> 13#include <asm/cpu.h> 14#include <asm/global_data.h> 15#include <asm/gpio.h> 16#include <asm/io.h> 17#include <asm/pci.h> 18#include <asm/arch/gpio.h> 19#include <dt-bindings/gpio/x86-gpio.h> 20#include <dm/pinctrl.h> 21#include <dm/uclass-internal.h> 22 23DECLARE_GLOBAL_DATA_PTR; 24 25enum { 26 MAX_GPIOS = 95, 27}; 28 29#define PIRQ_SHIFT 16 30#define CONF_MASK 0xffff 31 32struct pin_info { 33 int node; 34 int phandle; 35 bool mode_gpio; 36 bool dir_input; 37 bool invert; 38 bool trigger_level; 39 bool output_high; 40 bool sense_disable; 41 bool owner_gpio; 42 bool route_smi; 43 bool irq_enable; 44 bool reset_rsmrst; 45 bool pirq_apic_route; 46}; 47 48static int broadwell_pinctrl_read_configs(struct udevice *dev, 49 struct pin_info *conf, int max_pins) 50{ 51 const void *blob = gd->fdt_blob; 52 int count = 0; 53 int node; 54 55 debug("%s: starting\n", __func__); 56 for (node = fdt_first_subnode(blob, dev_of_offset(dev)); 57 node > 0; 58 node = fdt_next_subnode(blob, node)) { 59 int phandle = fdt_get_phandle(blob, node); 60 61 if (!phandle) 62 continue; 63 if (count == max_pins) 64 return -ENOSPC; 65 66 /* We've found a new configuration */ 67 memset(conf, '\0', sizeof(*conf)); 68 conf->node = node; 69 conf->phandle = phandle; 70 conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio"); 71 if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT) 72 conf->dir_input = true; 73 conf->invert = fdtdec_get_bool(blob, node, "invert"); 74 if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL) 75 conf->trigger_level = true; 76 if (fdtdec_get_int(blob, node, "output-value", -1) == 1) 77 conf->output_high = true; 78 conf->sense_disable = fdtdec_get_bool(blob, node, 79 "sense-disable"); 80 if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO) 81 conf->owner_gpio = true; 82 if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI) 83 conf->route_smi = true; 84 conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable"); 85 conf->reset_rsmrst = fdtdec_get_bool(blob, node, 86 "reset-rsmrst"); 87 if (fdtdec_get_int(blob, node, "pirq-apic", -1) == 88 PIRQ_APIC_ROUTE) 89 conf->pirq_apic_route = true; 90 debug("config: phandle=%d\n", phandle); 91 count++; 92 conf++; 93 } 94 debug("%s: Found %d configurations\n", __func__, count); 95 96 return count; 97} 98 99static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf, 100 int conf_count, int phandle) 101{ 102 int i; 103 104 for (i = 0; i < conf_count; i++) { 105 if (conf[i].phandle == phandle) 106 return i; 107 } 108 109 return -ENOENT; 110} 111 112static int broadwell_pinctrl_read_pins(struct udevice *dev, 113 struct pin_info *conf, int conf_count, int gpio_conf[], 114 int num_gpios) 115{ 116 const void *blob = gd->fdt_blob; 117 int count = 0; 118 int node; 119 120 for (node = fdt_first_subnode(blob, dev_of_offset(dev)); 121 node > 0; 122 node = fdt_next_subnode(blob, node)) { 123 int len, i; 124 const u32 *prop = fdt_getprop(blob, node, "config", &len); 125 126 if (!prop) 127 continue; 128 129 /* There are three cells per pin */ 130 count = len / (sizeof(u32) * 3); 131 debug("Found %d GPIOs to configure\n", count); 132 for (i = 0; i < count; i++) { 133 uint gpio = fdt32_to_cpu(prop[i * 3]); 134 uint phandle = fdt32_to_cpu(prop[i * 3 + 1]); 135 int val; 136 137 if (gpio >= num_gpios) { 138 debug("%s: GPIO %d out of range\n", __func__, 139 gpio); 140 return -EDOM; 141 } 142 val = broadwell_pinctrl_lookup_phandle(conf, conf_count, 143 phandle); 144 if (val < 0) { 145 debug("%s: Cannot find phandle %d\n", __func__, 146 phandle); 147 return -EINVAL; 148 } 149 gpio_conf[gpio] = val | 150 fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT; 151 } 152 } 153 154 return 0; 155} 156 157static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs, 158 struct pin_info *pin_info, 159 int gpio_conf[], int count) 160{ 161 u32 owner_gpio[GPIO_BANKS] = {0}; 162 u32 route_smi[GPIO_BANKS] = {0}; 163 u32 irq_enable[GPIO_BANKS] = {0}; 164 u32 reset_rsmrst[GPIO_BANKS] = {0}; 165 u32 pirq2apic = 0; 166 int set, bit, gpio = 0; 167 168 for (gpio = 0; gpio < MAX_GPIOS; gpio++) { 169 int confnum = gpio_conf[gpio] & CONF_MASK; 170 struct pin_info *pin = &pin_info[confnum]; 171 u32 val; 172 173 val = pin->mode_gpio << CONFA_MODE_SHIFT | 174 pin->dir_input << CONFA_DIR_SHIFT | 175 pin->invert << CONFA_INVERT_SHIFT | 176 pin->trigger_level << CONFA_TRIGGER_SHIFT | 177 pin->output_high << CONFA_OUTPUT_SHIFT; 178 outl(val, ®s->config[gpio].conf_a); 179 outl(pin->sense_disable << CONFB_SENSE_SHIFT, 180 ®s->config[gpio].conf_b); 181 182 /* Determine set and bit based on GPIO number */ 183 set = gpio / GPIO_PER_BANK; 184 bit = gpio % GPIO_PER_BANK; 185 186 /* Apply settings to set specific bits */ 187 owner_gpio[set] |= pin->owner_gpio << bit; 188 route_smi[set] |= pin->route_smi << bit; 189 irq_enable[set] |= pin->irq_enable << bit; 190 reset_rsmrst[set] |= pin->reset_rsmrst << bit; 191 192 /* PIRQ to IO-APIC map */ 193 if (pin->pirq_apic_route) 194 pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT; 195 debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n", 196 gpio, confnum, pin->mode_gpio, pin->dir_input, 197 pin->output_high); 198 } 199 200 for (set = 0; set < GPIO_BANKS; set++) { 201 outl(owner_gpio[set], ®s->own[set]); 202 outl(route_smi[set], ®s->gpi_route[set]); 203 outl(irq_enable[set], ®s->gpi_ie[set]); 204 outl(reset_rsmrst[set], ®s->rst_sel[set]); 205 } 206 207 outl(pirq2apic, ®s->pirq_to_ioxapic); 208} 209 210static int broadwell_pinctrl_probe(struct udevice *dev) 211{ 212 struct pch_lp_gpio_regs *regs; 213 struct pin_info conf[12]; 214 int gpio_conf[MAX_GPIOS]; 215 struct udevice *pch; 216 int conf_count; 217 u32 gpiobase; 218 int ret; 219 220 ret = uclass_find_first_device(UCLASS_PCH, &pch); 221 if (ret) 222 return ret; 223 if (!pch) 224 return -ENODEV; 225 debug("%s: start\n", __func__); 226 227 /* Only init once, before relocation */ 228 if (gd->flags & GD_FLG_RELOC) 229 return 0; 230 231 /* 232 * Get the memory/io base address to configure every pins. 233 * IOBASE is used to configure the mode/pads 234 * GPIOBASE is used to configure the direction and default value 235 */ 236 ret = pch_get_gpio_base(pch, &gpiobase); 237 if (ret) { 238 debug("%s: invalid GPIOBASE address (%08x)\n", __func__, 239 gpiobase); 240 return -EINVAL; 241 } 242 243 conf_count = broadwell_pinctrl_read_configs(dev, conf, 244 ARRAY_SIZE(conf)); 245 if (conf_count < 0) { 246 debug("%s: Cannot read configs: err=%d\n", __func__, ret); 247 return conf_count; 248 } 249 250 /* 251 * Assume that pin settings are provided for every pin. Pins not 252 * mentioned will get the first config mentioned in the list. 253 */ 254 ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf, 255 MAX_GPIOS); 256 if (ret) { 257 debug("%s: Cannot read pin settings: err=%d\n", __func__, ret); 258 return ret; 259 } 260 261 regs = (struct pch_lp_gpio_regs *)gpiobase; 262 broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf)); 263 264 debug("%s: done\n", __func__); 265 266 return 0; 267} 268 269static const struct udevice_id broadwell_pinctrl_match[] = { 270 { .compatible = "intel,x86-broadwell-pinctrl", 271 .data = X86_SYSCON_PINCONF }, 272 { /* sentinel */ } 273}; 274 275U_BOOT_DRIVER(broadwell_pinctrl) = { 276 .name = "broadwell_pinctrl", 277 .id = UCLASS_SYSCON, 278 .of_match = broadwell_pinctrl_match, 279 .probe = broadwell_pinctrl_probe, 280}; 281