1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6#include <common.h> 7#include <init.h> 8#include <mmc.h> 9#include <pci_ids.h> 10#include <asm/irq.h> 11#include <asm/mrccache.h> 12#include <asm/post.h> 13#include <asm/arch/iomap.h> 14#include <linux/bitops.h> 15 16/* GPIO SUS */ 17#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) 18#define GPIO_SUS_DFX5_CONF0 0x150 19#define BYT_TRIG_LVL BIT(24) 20#define BYT_TRIG_POS BIT(25) 21 22int arch_cpu_init(void) 23{ 24 post_code(POST_CPU_INIT); 25 26 return x86_cpu_init_f(); 27} 28 29int arch_misc_init(void) 30{ 31 if (!ll_boot_init()) 32 return 0; 33 34#ifdef CONFIG_ENABLE_MRC_CACHE 35 /* 36 * We intend not to check any return value here, as even MRC cache 37 * is not saved successfully, it is not a severe error that will 38 * prevent system from continuing to boot. 39 */ 40 mrccache_save(); 41#endif 42 43 /* 44 * For some unknown reason, FSP (gold4) for BayTrail configures 45 * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25). 46 * This does not cause any issue when Linux kernel runs w/ or w/o 47 * the pinctrl driver for BayTrail. However this causes unstable 48 * S3 resume if the pinctrl driver is included in the kernel build. 49 * As this pin keeps generating interrupts during an S3 resume, 50 * and there is no IRQ requester in the kernel to handle it, the 51 * kernel seems to hang and does not continue resuming. 52 * 53 * Clear the mysterious interrupt bits for this pin. 54 */ 55 clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0, 56 BYT_TRIG_LVL | BYT_TRIG_POS); 57 58 return 0; 59} 60