1/** @file */
2
3#ifndef _MACH_T186_CLK_T186_H
4#define _MACH_T186_CLK_T186_H
5
6/**
7 * @defgroup clock_ids Clock Identifiers
8 * @{
9 *   @defgroup extern_input external input clocks
10 *   @{
11 *     @def TEGRA186_CLK_OSC
12 *     @def TEGRA186_CLK_CLK_32K
13 *     @def TEGRA186_CLK_DTV_INPUT
14 *     @def TEGRA186_CLK_SOR0_PAD_CLKOUT
15 *     @def TEGRA186_CLK_SOR1_PAD_CLKOUT
16 *     @def TEGRA186_CLK_I2S1_SYNC_INPUT
17 *     @def TEGRA186_CLK_I2S2_SYNC_INPUT
18 *     @def TEGRA186_CLK_I2S3_SYNC_INPUT
19 *     @def TEGRA186_CLK_I2S4_SYNC_INPUT
20 *     @def TEGRA186_CLK_I2S5_SYNC_INPUT
21 *     @def TEGRA186_CLK_I2S6_SYNC_INPUT
22 *     @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
23 *   @}
24 *
25 *   @defgroup extern_output external output clocks
26 *   @{
27 *     @def TEGRA186_CLK_EXTPERIPH1
28 *     @def TEGRA186_CLK_EXTPERIPH2
29 *     @def TEGRA186_CLK_EXTPERIPH3
30 *     @def TEGRA186_CLK_EXTPERIPH4
31 *   @}
32 *
33 *   @defgroup display_clks display related clocks
34 *   @{
35 *     @def TEGRA186_CLK_CEC
36 *     @def TEGRA186_CLK_DSIC
37 *     @def TEGRA186_CLK_DSIC_LP
38 *     @def TEGRA186_CLK_DSID
39 *     @def TEGRA186_CLK_DSID_LP
40 *     @def TEGRA186_CLK_DPAUX1
41 *     @def TEGRA186_CLK_DPAUX
42 *     @def TEGRA186_CLK_HDA2HDMICODEC
43 *     @def TEGRA186_CLK_NVDISPLAY_DISP
44 *     @def TEGRA186_CLK_NVDISPLAY_DSC
45 *     @def TEGRA186_CLK_NVDISPLAY_P0
46 *     @def TEGRA186_CLK_NVDISPLAY_P1
47 *     @def TEGRA186_CLK_NVDISPLAY_P2
48 *     @def TEGRA186_CLK_NVDISPLAYHUB
49 *     @def TEGRA186_CLK_SOR_SAFE
50 *     @def TEGRA186_CLK_SOR0
51 *     @def TEGRA186_CLK_SOR0_OUT
52 *     @def TEGRA186_CLK_SOR1
53 *     @def TEGRA186_CLK_SOR1_OUT
54 *     @def TEGRA186_CLK_DSI
55 *     @def TEGRA186_CLK_MIPI_CAL
56 *     @def TEGRA186_CLK_DSIA_LP
57 *     @def TEGRA186_CLK_DSIB
58 *     @def TEGRA186_CLK_DSIB_LP
59 *   @}
60 *
61 *   @defgroup camera_clks camera related clocks
62 *   @{
63 *     @def TEGRA186_CLK_NVCSI
64 *     @def TEGRA186_CLK_NVCSILP
65 *     @def TEGRA186_CLK_VI
66 *   @}
67 *
68 *   @defgroup audio_clks audio related clocks
69 *   @{
70 *     @def TEGRA186_CLK_ACLK
71 *     @def TEGRA186_CLK_ADSP
72 *     @def TEGRA186_CLK_ADSPNEON
73 *     @def TEGRA186_CLK_AHUB
74 *     @def TEGRA186_CLK_APE
75 *     @def TEGRA186_CLK_APB2APE
76 *     @def TEGRA186_CLK_AUD_MCLK
77 *     @def TEGRA186_CLK_DMIC1
78 *     @def TEGRA186_CLK_DMIC2
79 *     @def TEGRA186_CLK_DMIC3
80 *     @def TEGRA186_CLK_DMIC4
81 *     @def TEGRA186_CLK_DSPK1
82 *     @def TEGRA186_CLK_DSPK2
83 *     @def TEGRA186_CLK_HDA
84 *     @def TEGRA186_CLK_HDA2CODEC_2X
85 *     @def TEGRA186_CLK_I2S1
86 *     @def TEGRA186_CLK_I2S2
87 *     @def TEGRA186_CLK_I2S3
88 *     @def TEGRA186_CLK_I2S4
89 *     @def TEGRA186_CLK_I2S5
90 *     @def TEGRA186_CLK_I2S6
91 *     @def TEGRA186_CLK_MAUD
92 *     @def TEGRA186_CLK_PLL_A_OUT0
93 *     @def TEGRA186_CLK_SPDIF_DOUBLER
94 *     @def TEGRA186_CLK_SPDIF_IN
95 *     @def TEGRA186_CLK_SPDIF_OUT
96 *     @def TEGRA186_CLK_SYNC_DMIC1
97 *     @def TEGRA186_CLK_SYNC_DMIC2
98 *     @def TEGRA186_CLK_SYNC_DMIC3
99 *     @def TEGRA186_CLK_SYNC_DMIC4
100 *     @def TEGRA186_CLK_SYNC_DMIC5
101 *     @def TEGRA186_CLK_SYNC_DSPK1
102 *     @def TEGRA186_CLK_SYNC_DSPK2
103 *     @def TEGRA186_CLK_SYNC_I2S1
104 *     @def TEGRA186_CLK_SYNC_I2S2
105 *     @def TEGRA186_CLK_SYNC_I2S3
106 *     @def TEGRA186_CLK_SYNC_I2S4
107 *     @def TEGRA186_CLK_SYNC_I2S5
108 *     @def TEGRA186_CLK_SYNC_I2S6
109 *     @def TEGRA186_CLK_SYNC_SPDIF
110 *   @}
111 *
112 *   @defgroup uart_clks UART clocks
113 *   @{
114 *     @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
115 *     @def TEGRA186_CLK_UARTA
116 *     @def TEGRA186_CLK_UARTB
117 *     @def TEGRA186_CLK_UARTC
118 *     @def TEGRA186_CLK_UARTD
119 *     @def TEGRA186_CLK_UARTE
120 *     @def TEGRA186_CLK_UARTF
121 *     @def TEGRA186_CLK_UARTG
122 *     @def TEGRA186_CLK_UART_FST_MIPI_CAL
123 *   @}
124 *
125 *   @defgroup i2c_clks I2C clocks
126 *   @{
127 *     @def TEGRA186_CLK_AON_I2C_SLOW
128 *     @def TEGRA186_CLK_I2C1
129 *     @def TEGRA186_CLK_I2C2
130 *     @def TEGRA186_CLK_I2C3
131 *     @def TEGRA186_CLK_I2C4
132 *     @def TEGRA186_CLK_I2C5
133 *     @def TEGRA186_CLK_I2C6
134 *     @def TEGRA186_CLK_I2C8
135 *     @def TEGRA186_CLK_I2C9
136 *     @def TEGRA186_CLK_I2C1
137 *     @def TEGRA186_CLK_I2C12
138 *     @def TEGRA186_CLK_I2C13
139 *     @def TEGRA186_CLK_I2C14
140 *     @def TEGRA186_CLK_I2C_SLOW
141 *     @def TEGRA186_CLK_VI_I2C
142 *   @}
143 *
144 *   @defgroup spi_clks SPI clocks
145 *   @{
146 *     @def TEGRA186_CLK_SPI1
147 *     @def TEGRA186_CLK_SPI2
148 *     @def TEGRA186_CLK_SPI3
149 *     @def TEGRA186_CLK_SPI4
150 *   @}
151 *
152 *   @defgroup storage storage related clocks
153 *   @{
154 *     @def TEGRA186_CLK_SATA
155 *     @def TEGRA186_CLK_SATA_OOB
156 *     @def TEGRA186_CLK_SATA_IOBIST
157 *     @def TEGRA186_CLK_SDMMC_LEGACY_TM
158 *     @def TEGRA186_CLK_SDMMC1
159 *     @def TEGRA186_CLK_SDMMC2
160 *     @def TEGRA186_CLK_SDMMC3
161 *     @def TEGRA186_CLK_SDMMC4
162 *     @def TEGRA186_CLK_QSPI
163 *     @def TEGRA186_CLK_QSPI_OUT
164 *     @def TEGRA186_CLK_UFSDEV_REF
165 *     @def TEGRA186_CLK_UFSHC
166 *   @}
167 *
168 *   @defgroup pwm_clks PWM clocks
169 *   @{
170 *     @def TEGRA186_CLK_PWM1
171 *     @def TEGRA186_CLK_PWM2
172 *     @def TEGRA186_CLK_PWM3
173 *     @def TEGRA186_CLK_PWM4
174 *     @def TEGRA186_CLK_PWM5
175 *     @def TEGRA186_CLK_PWM6
176 *     @def TEGRA186_CLK_PWM7
177 *     @def TEGRA186_CLK_PWM8
178 *   @}
179 *
180 *   @defgroup plls PLLs and related clocks
181 *   @{
182 *     @def TEGRA186_CLK_PLLREFE_OUT_GATED
183 *     @def TEGRA186_CLK_PLLREFE_OUT1
184 *     @def TEGRA186_CLK_PLLD_OUT1
185 *     @def TEGRA186_CLK_PLLP_OUT0
186 *     @def TEGRA186_CLK_PLLP_OUT5
187 *     @def TEGRA186_CLK_PLLA
188 *     @def TEGRA186_CLK_PLLE_PWRSEQ
189 *     @def TEGRA186_CLK_PLLA_OUT1
190 *     @def TEGRA186_CLK_PLLREFE_REF
191 *     @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
192 *     @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
193 *     @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
194 *     @def TEGRA186_CLK_PLLREFE_PEX
195 *     @def TEGRA186_CLK_PLLREFE_IDDQ
196 *     @def TEGRA186_CLK_PLLC_OUT_AON
197 *     @def TEGRA186_CLK_PLLC_OUT_ISP
198 *     @def TEGRA186_CLK_PLLC_OUT_VE
199 *     @def TEGRA186_CLK_PLLC4_OUT
200 *     @def TEGRA186_CLK_PLLREFE_OUT
201 *     @def TEGRA186_CLK_PLLREFE_PLL_REF
202 *     @def TEGRA186_CLK_PLLE
203 *     @def TEGRA186_CLK_PLLC
204 *     @def TEGRA186_CLK_PLLP
205 *     @def TEGRA186_CLK_PLLD
206 *     @def TEGRA186_CLK_PLLD2
207 *     @def TEGRA186_CLK_PLLREFE_VCO
208 *     @def TEGRA186_CLK_PLLC2
209 *     @def TEGRA186_CLK_PLLC3
210 *     @def TEGRA186_CLK_PLLDP
211 *     @def TEGRA186_CLK_PLLC4_VCO
212 *     @def TEGRA186_CLK_PLLA1
213 *     @def TEGRA186_CLK_PLLNVCSI
214 *     @def TEGRA186_CLK_PLLDISPHUB
215 *     @def TEGRA186_CLK_PLLD3
216 *     @def TEGRA186_CLK_PLLBPMPCAM
217 *     @def TEGRA186_CLK_PLLAON
218 *     @def TEGRA186_CLK_PLLU
219 *     @def TEGRA186_CLK_PLLC4_VCO_DIV2
220 *     @def TEGRA186_CLK_PLL_REF
221 *     @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
222 *     @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
223 *     @def TEGRA186_CLK_PLL_U_48M
224 *     @def TEGRA186_CLK_PLL_U_480M
225 *     @def TEGRA186_CLK_PLLC4_OUT0
226 *     @def TEGRA186_CLK_PLLC4_OUT1
227 *     @def TEGRA186_CLK_PLLC4_OUT2
228 *     @def TEGRA186_CLK_PLLC4_OUT_MUX
229 *     @def TEGRA186_CLK_DFLLDISP_DIV
230 *     @def TEGRA186_CLK_PLLDISPHUB_DIV
231 *     @def TEGRA186_CLK_PLLP_DIV8
232 *   @}
233 *
234 *   @defgroup nafll_clks NAFLL clock sources
235 *   @{
236 *     @def TEGRA186_CLK_NAFLL_AXI_CBB
237 *     @def TEGRA186_CLK_NAFLL_BCPU
238 *     @def TEGRA186_CLK_NAFLL_BPMP
239 *     @def TEGRA186_CLK_NAFLL_DISP
240 *     @def TEGRA186_CLK_NAFLL_GPU
241 *     @def TEGRA186_CLK_NAFLL_ISP
242 *     @def TEGRA186_CLK_NAFLL_MCPU
243 *     @def TEGRA186_CLK_NAFLL_NVDEC
244 *     @def TEGRA186_CLK_NAFLL_NVENC
245 *     @def TEGRA186_CLK_NAFLL_NVJPG
246 *     @def TEGRA186_CLK_NAFLL_SCE
247 *     @def TEGRA186_CLK_NAFLL_SE
248 *     @def TEGRA186_CLK_NAFLL_TSEC
249 *     @def TEGRA186_CLK_NAFLL_TSECB
250 *     @def TEGRA186_CLK_NAFLL_VI
251 *     @def TEGRA186_CLK_NAFLL_VIC
252 *   @}
253 *
254 *   @defgroup mphy MPHY related clocks
255 *   @{
256 *     @def TEGRA186_CLK_MPHY_L0_RX_SYMB
257 *     @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
258 *     @def TEGRA186_CLK_MPHY_L0_TX_SYMB
259 *     @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
260 *     @def TEGRA186_CLK_MPHY_L0_RX_ANA
261 *     @def TEGRA186_CLK_MPHY_L1_RX_ANA
262 *     @def TEGRA186_CLK_MPHY_IOBIST
263 *     @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
264 *     @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
265 *   @}
266 *
267 *   @defgroup eavb EAVB related clocks
268 *   @{
269 *     @def TEGRA186_CLK_EQOS_AXI
270 *     @def TEGRA186_CLK_EQOS_PTP_REF
271 *     @def TEGRA186_CLK_EQOS_RX
272 *     @def TEGRA186_CLK_EQOS_RX_INPUT
273 *     @def TEGRA186_CLK_EQOS_TX
274 *   @}
275 *
276 *   @defgroup usb USB related clocks
277 *   @{
278 *     @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
279 *     @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
280 *     @def TEGRA186_CLK_HSIC_TRK
281 *     @def TEGRA186_CLK_USB2_TRK
282 *     @def TEGRA186_CLK_USB2_HSIC_TRK
283 *     @def TEGRA186_CLK_XUSB_CORE_SS
284 *     @def TEGRA186_CLK_XUSB_CORE_DEV
285 *     @def TEGRA186_CLK_XUSB_FALCON
286 *     @def TEGRA186_CLK_XUSB_FS
287 *     @def TEGRA186_CLK_XUSB
288 *     @def TEGRA186_CLK_XUSB_DEV
289 *     @def TEGRA186_CLK_XUSB_HOST
290 *     @def TEGRA186_CLK_XUSB_SS
291 *   @}
292 *
293 *   @defgroup bigblock compute block related clocks
294 *   @{
295 *     @def TEGRA186_CLK_GPCCLK
296 *     @def TEGRA186_CLK_GPC2CLK
297 *     @def TEGRA186_CLK_GPU
298 *     @def TEGRA186_CLK_HOST1X
299 *     @def TEGRA186_CLK_ISP
300 *     @def TEGRA186_CLK_NVDEC
301 *     @def TEGRA186_CLK_NVENC
302 *     @def TEGRA186_CLK_NVJPG
303 *     @def TEGRA186_CLK_SE
304 *     @def TEGRA186_CLK_TSEC
305 *     @def TEGRA186_CLK_TSECB
306 *     @def TEGRA186_CLK_VIC
307 *   @}
308 *
309 *   @defgroup can CAN bus related clocks
310 *   @{
311 *     @def TEGRA186_CLK_CAN1
312 *     @def TEGRA186_CLK_CAN1_HOST
313 *     @def TEGRA186_CLK_CAN2
314 *     @def TEGRA186_CLK_CAN2_HOST
315 *   @}
316 *
317 *   @defgroup system basic system clocks
318 *   @{
319 *     @def TEGRA186_CLK_ACTMON
320 *     @def TEGRA186_CLK_AON_APB
321 *     @def TEGRA186_CLK_AON_CPU_NIC
322 *     @def TEGRA186_CLK_AON_NIC
323 *     @def TEGRA186_CLK_AXI_CBB
324 *     @def TEGRA186_CLK_BPMP_APB
325 *     @def TEGRA186_CLK_BPMP_CPU_NIC
326 *     @def TEGRA186_CLK_BPMP_NIC_RATE
327 *     @def TEGRA186_CLK_CLK_M
328 *     @def TEGRA186_CLK_EMC
329 *     @def TEGRA186_CLK_MSS_ENCRYPT
330 *     @def TEGRA186_CLK_SCE_APB
331 *     @def TEGRA186_CLK_SCE_CPU_NIC
332 *     @def TEGRA186_CLK_SCE_NIC
333 *     @def TEGRA186_CLK_TSC
334 *   @}
335 *
336 *   @defgroup pcie_clks PCIe related clocks
337 *   @{
338 *     @def TEGRA186_CLK_AFI
339 *     @def TEGRA186_CLK_PCIE
340 *     @def TEGRA186_CLK_PCIE2_IOBIST
341 *     @def TEGRA186_CLK_PCIERX0
342 *     @def TEGRA186_CLK_PCIERX1
343 *     @def TEGRA186_CLK_PCIERX2
344 *     @def TEGRA186_CLK_PCIERX3
345 *     @def TEGRA186_CLK_PCIERX4
346 *   @}
347 */
348
349/** @brief output of gate CLK_ENB_FUSE */
350#define TEGRA186_CLK_FUSE 0
351/**
352 * @brief It's not what you think
353 * @details output of gate CLK_ENB_GPU. This output connects to the GPU
354 * pwrclk. @warning: This is almost certainly not the clock you think
355 * it is. If you're looking for the clock of the graphics engine, see
356 * TEGRA186_GPCCLK
357 */
358#define TEGRA186_CLK_GPU 1
359/** @brief output of gate CLK_ENB_PCIE */
360#define TEGRA186_CLK_PCIE 3
361/** @brief output of the divider IPFS_CLK_DIVISOR */
362#define TEGRA186_CLK_AFI 4
363/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
364#define TEGRA186_CLK_PCIE2_IOBIST 5
365/** @brief output of gate CLK_ENB_PCIERX0*/
366#define TEGRA186_CLK_PCIERX0 6
367/** @brief output of gate CLK_ENB_PCIERX1*/
368#define TEGRA186_CLK_PCIERX1 7
369/** @brief output of gate CLK_ENB_PCIERX2*/
370#define TEGRA186_CLK_PCIERX2 8
371/** @brief output of gate CLK_ENB_PCIERX3*/
372#define TEGRA186_CLK_PCIERX3 9
373/** @brief output of gate CLK_ENB_PCIERX4*/
374#define TEGRA186_CLK_PCIERX4 10
375/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
376#define TEGRA186_CLK_PLLC_OUT_ISP 11
377/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
378#define TEGRA186_CLK_PLLC_OUT_VE 12
379/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
380#define TEGRA186_CLK_PLLC_OUT_AON 13
381/** @brief output of gate CLK_ENB_SOR_SAFE */
382#define TEGRA186_CLK_SOR_SAFE 39
383/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
384#define TEGRA186_CLK_I2S2 42
385/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
386#define TEGRA186_CLK_I2S3 43
387/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
388#define TEGRA186_CLK_SPDIF_IN 44
389/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
390#define TEGRA186_CLK_SPDIF_DOUBLER 45
391/**  @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
392#define TEGRA186_CLK_SPI3 46
393/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
394#define TEGRA186_CLK_I2C1 47
395/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
396#define TEGRA186_CLK_I2C5 48
397/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
398#define TEGRA186_CLK_SPI1 49
399/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
400#define TEGRA186_CLK_ISP 50
401/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
402#define TEGRA186_CLK_VI 51
403/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
404#define TEGRA186_CLK_SDMMC1 52
405/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
406#define TEGRA186_CLK_SDMMC2 53
407/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
408#define TEGRA186_CLK_SDMMC4 54
409/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
410#define TEGRA186_CLK_UARTA 55
411/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
412#define TEGRA186_CLK_UARTB 56
413/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
414#define TEGRA186_CLK_HOST1X 57
415/**
416 * @brief controls the EMC clock frequency.
417 * @details Doing a clk_set_rate on this clock will select the
418 * appropriate clock source, program the source rate and execute a
419 * specific sequence to switch to the new clock source for both memory
420 * controllers. This can be used to control the balance between memory
421 * throughput and memory controller power.
422 */
423#define TEGRA186_CLK_EMC 58
424/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
425#define TEGRA186_CLK_EXTPERIPH4 73
426/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
427#define TEGRA186_CLK_SPI4 74
428/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
429#define TEGRA186_CLK_I2C3 75
430/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
431#define TEGRA186_CLK_SDMMC3 76
432/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
433#define TEGRA186_CLK_UARTD 77
434/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
435#define TEGRA186_CLK_I2S1 79
436/** output of gate CLK_ENB_DTV */
437#define TEGRA186_CLK_DTV 80
438/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
439#define TEGRA186_CLK_TSEC 81
440/** @brief output of gate CLK_ENB_DP2 */
441#define TEGRA186_CLK_DP2 82
442/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
443#define TEGRA186_CLK_I2S4 84
444/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
445#define TEGRA186_CLK_I2S5 85
446/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
447#define TEGRA186_CLK_I2C4 86
448/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
449#define TEGRA186_CLK_AHUB 87
450/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
451#define TEGRA186_CLK_HDA2CODEC_2X 88
452/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
453#define TEGRA186_CLK_EXTPERIPH1 89
454/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
455#define TEGRA186_CLK_EXTPERIPH2 90
456/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
457#define TEGRA186_CLK_EXTPERIPH3 91
458/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
459#define TEGRA186_CLK_I2C_SLOW 92
460/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
461#define TEGRA186_CLK_SOR1 93
462/** @brief output of gate CLK_ENB_CEC */
463#define TEGRA186_CLK_CEC 94
464/** @brief output of gate CLK_ENB_DPAUX1 */
465#define TEGRA186_CLK_DPAUX1 95
466/** @brief output of gate CLK_ENB_DPAUX */
467#define TEGRA186_CLK_DPAUX 96
468/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
469#define TEGRA186_CLK_SOR0 97
470/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
471#define TEGRA186_CLK_HDA2HDMICODEC 98
472/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
473#define TEGRA186_CLK_SATA 99
474/** @brief output of gate CLK_ENB_SATA_OOB */
475#define TEGRA186_CLK_SATA_OOB 100
476/** @brief output of gate CLK_ENB_SATA_IOBIST */
477#define TEGRA186_CLK_SATA_IOBIST 101
478/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
479#define TEGRA186_CLK_HDA 102
480/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
481#define TEGRA186_CLK_SE 103
482/** @brief output of gate CLK_ENB_APB2APE */
483#define TEGRA186_CLK_APB2APE 104
484/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
485#define TEGRA186_CLK_APE 105
486/** @brief output of gate CLK_ENB_IQC1 */
487#define TEGRA186_CLK_IQC1 106
488/** @brief output of gate CLK_ENB_IQC2 */
489#define TEGRA186_CLK_IQC2 107
490/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
491#define TEGRA186_CLK_PLLREFE_OUT 108
492/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
493#define TEGRA186_CLK_PLLREFE_PLL_REF 109
494/** @brief output of gate CLK_ENB_PLLC4_OUT */
495#define TEGRA186_CLK_PLLC4_OUT 110
496/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
497#define TEGRA186_CLK_XUSB 111
498/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
499#define TEGRA186_CLK_XUSB_DEV 112
500/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
501#define TEGRA186_CLK_XUSB_HOST 113
502/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
503#define TEGRA186_CLK_XUSB_SS 114
504/** @brief output of gate CLK_ENB_DSI */
505#define TEGRA186_CLK_DSI 115
506/** @brief output of gate CLK_ENB_MIPI_CAL */
507#define TEGRA186_CLK_MIPI_CAL 116
508/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
509#define TEGRA186_CLK_DSIA_LP 117
510/** @brief output of gate CLK_ENB_DSIB */
511#define TEGRA186_CLK_DSIB 118
512/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
513#define TEGRA186_CLK_DSIB_LP 119
514/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
515#define TEGRA186_CLK_DMIC1 122
516/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
517#define TEGRA186_CLK_DMIC2 123
518/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
519#define TEGRA186_CLK_AUD_MCLK 124
520/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
521#define TEGRA186_CLK_I2C6 125
522/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
523#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
524/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
525#define TEGRA186_CLK_VIC 127
526/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
527#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
528/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
529#define TEGRA186_CLK_NVDEC 129
530/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
531#define TEGRA186_CLK_NVJPG 130
532/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
533#define TEGRA186_CLK_NVENC 131
534/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
535#define TEGRA186_CLK_QSPI 132
536/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
537#define TEGRA186_CLK_VI_I2C 133
538/** @brief output of gate CLK_ENB_HSIC_TRK */
539#define TEGRA186_CLK_HSIC_TRK 134
540/** @brief output of gate CLK_ENB_USB2_TRK */
541#define TEGRA186_CLK_USB2_TRK 135
542/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
543#define TEGRA186_CLK_MAUD 136
544/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
545#define TEGRA186_CLK_TSECB 137
546/** @brief output of gate CLK_ENB_ADSP */
547#define TEGRA186_CLK_ADSP 138
548/** @brief output of gate CLK_ENB_ADSPNEON */
549#define TEGRA186_CLK_ADSPNEON 139
550/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
551#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
552/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
553#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
554/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
555#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
556/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
557#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
558/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
559#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
560/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
561#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
562/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
563#define TEGRA186_CLK_MPHY_IOBIST 146
564/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
565#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
566/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
567#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
568/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
569#define TEGRA186_CLK_AXI_CBB 149
570/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
571#define TEGRA186_CLK_DMIC3 150
572/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
573#define TEGRA186_CLK_DMIC4 151
574/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
575#define TEGRA186_CLK_DSPK1 152
576/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
577#define TEGRA186_CLK_DSPK2 153
578/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
579#define TEGRA186_CLK_I2S6 154
580/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
581#define TEGRA186_CLK_NVDISPLAY_P0 155
582/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
583#define TEGRA186_CLK_NVDISPLAY_DISP 156
584/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
585#define TEGRA186_CLK_NVDISPLAY_DSC 157
586/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
587#define TEGRA186_CLK_NVDISPLAYHUB 158
588/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
589#define TEGRA186_CLK_NVDISPLAY_P1 159
590/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
591#define TEGRA186_CLK_NVDISPLAY_P2 160
592/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
593#define TEGRA186_CLK_TACH 166
594/** @brief output of gate CLK_ENB_EQOS */
595#define TEGRA186_CLK_EQOS_AXI 167
596/** @brief output of gate CLK_ENB_EQOS_RX */
597#define TEGRA186_CLK_EQOS_RX 168
598/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
599#define TEGRA186_CLK_UFSHC 178
600/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
601#define TEGRA186_CLK_UFSDEV_REF 179
602/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
603#define TEGRA186_CLK_NVCSI 180
604/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
605#define TEGRA186_CLK_NVCSILP 181
606/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
607#define TEGRA186_CLK_I2C7 182
608/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
609#define TEGRA186_CLK_I2C9 183
610/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
611#define TEGRA186_CLK_I2C12 184
612/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
613#define TEGRA186_CLK_I2C13 185
614/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
615#define TEGRA186_CLK_I2C14 186
616/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
617#define TEGRA186_CLK_PWM1 187
618/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
619#define TEGRA186_CLK_PWM2 188
620/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
621#define TEGRA186_CLK_PWM3 189
622/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
623#define TEGRA186_CLK_PWM5 190
624/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
625#define TEGRA186_CLK_PWM6 191
626/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
627#define TEGRA186_CLK_PWM7 192
628/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
629#define TEGRA186_CLK_PWM8 193
630/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
631#define TEGRA186_CLK_UARTE 194
632/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
633#define TEGRA186_CLK_UARTF 195
634/** @deprecated */
635#define TEGRA186_CLK_DBGAPB 196
636/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
637#define TEGRA186_CLK_BPMP_CPU_NIC 197
638/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
639#define TEGRA186_CLK_BPMP_APB 199
640/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
641#define TEGRA186_CLK_ACTMON 201
642/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
643#define TEGRA186_CLK_AON_CPU_NIC 208
644/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
645#define TEGRA186_CLK_CAN1 210
646/** @brief output of gate CLK_ENB_CAN1_HOST */
647#define TEGRA186_CLK_CAN1_HOST 211
648/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
649#define TEGRA186_CLK_CAN2 212
650/** @brief output of gate CLK_ENB_CAN2_HOST */
651#define TEGRA186_CLK_CAN2_HOST 213
652/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
653#define TEGRA186_CLK_AON_APB 214
654/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
655#define TEGRA186_CLK_UARTC 215
656/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
657#define TEGRA186_CLK_UARTG 216
658/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
659#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
660/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
661#define TEGRA186_CLK_I2C2 218
662/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
663#define TEGRA186_CLK_I2C8 219
664/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
665#define TEGRA186_CLK_I2C10 220
666/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
667#define TEGRA186_CLK_AON_I2C_SLOW 221
668/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
669#define TEGRA186_CLK_SPI2 222
670/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
671#define TEGRA186_CLK_DMIC5 223
672/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
673#define TEGRA186_CLK_AON_TOUCH 224
674/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
675#define TEGRA186_CLK_PWM4 225
676/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
677#define TEGRA186_CLK_TSC 226
678/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
679#define TEGRA186_CLK_MSS_ENCRYPT 227
680/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
681#define TEGRA186_CLK_SCE_CPU_NIC 228
682/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
683#define TEGRA186_CLK_SCE_APB 230
684/** @brief output of gate CLK_ENB_DSIC */
685#define TEGRA186_CLK_DSIC 231
686/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
687#define TEGRA186_CLK_DSIC_LP 232
688/** @brief output of gate CLK_ENB_DSID */
689#define TEGRA186_CLK_DSID 233
690/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
691#define TEGRA186_CLK_DSID_LP 234
692/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
693#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
694/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
695#define TEGRA186_CLK_SPDIF_OUT 238
696/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
697#define TEGRA186_CLK_EQOS_PTP_REF 239
698/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
699#define TEGRA186_CLK_EQOS_TX 240
700/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
701#define TEGRA186_CLK_USB2_HSIC_TRK 241
702/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
703#define TEGRA186_CLK_XUSB_CORE_SS 242
704/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
705#define TEGRA186_CLK_XUSB_CORE_DEV 243
706/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
707#define TEGRA186_CLK_XUSB_FALCON 244
708/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
709#define TEGRA186_CLK_XUSB_FS 245
710/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
711#define TEGRA186_CLK_PLL_A_OUT0 246
712/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
713#define TEGRA186_CLK_SYNC_I2S1 247
714/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
715#define TEGRA186_CLK_SYNC_I2S2 248
716/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
717#define TEGRA186_CLK_SYNC_I2S3 249
718/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
719#define TEGRA186_CLK_SYNC_I2S4 250
720/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
721#define TEGRA186_CLK_SYNC_I2S5 251
722/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
723#define TEGRA186_CLK_SYNC_I2S6 252
724/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
725#define TEGRA186_CLK_SYNC_DSPK1 253
726/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
727#define TEGRA186_CLK_SYNC_DSPK2 254
728/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
729#define TEGRA186_CLK_SYNC_DMIC1 255
730/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
731#define TEGRA186_CLK_SYNC_DMIC2 256
732/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
733#define TEGRA186_CLK_SYNC_DMIC3 257
734/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
735#define TEGRA186_CLK_SYNC_DMIC4 259
736/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
737#define TEGRA186_CLK_SYNC_SPDIF 260
738/** @brief output of gate CLK_ENB_PLLREFE_OUT */
739#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
740/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
741  *      * VCO/pdiv defined by this clock object
742  *      * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
743  */
744#define TEGRA186_CLK_PLLREFE_OUT1 262
745#define TEGRA186_CLK_PLLD_OUT1 267
746/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
747#define TEGRA186_CLK_PLLP_OUT0 269
748/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
749#define TEGRA186_CLK_PLLP_OUT5 270
750/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
751#define TEGRA186_CLK_PLLA 271
752/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
753#define TEGRA186_CLK_ACLK 273
754/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
755#define TEGRA186_CLK_PLL_U_48M 274
756/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
757#define TEGRA186_CLK_PLL_U_480M 275
758/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
759#define TEGRA186_CLK_PLLC4_OUT0 276
760/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
761#define TEGRA186_CLK_PLLC4_OUT1 277
762/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
763#define TEGRA186_CLK_PLLC4_OUT2 278
764/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
765#define TEGRA186_CLK_PLLC4_OUT_MUX 279
766/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
767#define TEGRA186_CLK_DFLLDISP_DIV 284
768/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
769#define TEGRA186_CLK_PLLDISPHUB_DIV 285
770/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
771#define TEGRA186_CLK_PLLP_DIV8 286
772/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
773#define TEGRA186_CLK_BPMP_NIC 287
774/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
775#define TEGRA186_CLK_PLL_A_OUT1 288
776/** @deprecated */
777#define TEGRA186_CLK_GPC2CLK 289
778/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
779#define TEGRA186_CLK_KFUSE 293
780/**
781 * @brief controls the PLLE hardware sequencer.
782 * @details This clock only has enable and disable methods. When the
783 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
784 * hw based on the control signals from the PCIe, SATA and XUSB
785 * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
786 * is controlled by sw using clk_enable/clk_disable on
787 * TEGRA186_CLK_PLLE.
788 */
789#define TEGRA186_CLK_PLLE_PWRSEQ 294
790/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
791#define TEGRA186_CLK_PLLREFE_REF 295
792/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
793#define TEGRA186_CLK_SOR0_OUT 296
794/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
795#define TEGRA186_CLK_SOR1_OUT 297
796/** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
797#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
798/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
799#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
800/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
801#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
802/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
803#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
804/** @brief controls the UPHY_PLL0 hardware sqeuencer */
805#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
806/** @brief controls the UPHY_PLL1 hardware sqeuencer */
807#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
808/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
809#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
810/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
811#define TEGRA186_CLK_PLLREFE_PEX 307
812/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
813#define TEGRA186_CLK_PLLREFE_IDDQ 308
814/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
815#define TEGRA186_CLK_QSPI_OUT 309
816/**
817 * @brief GPC2CLK-div-2
818 * @details fixed /2 divider. Output frequency is
819 * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
820 * frequency at which the GPU graphics engine runs. */
821#define TEGRA186_CLK_GPCCLK 310
822/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
823#define TEGRA186_CLK_AON_NIC 450
824/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
825#define TEGRA186_CLK_SCE_NIC 451
826/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
827#define TEGRA186_CLK_PLLE 512
828/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
829#define TEGRA186_CLK_PLLC 513
830/** Fixed 408MHz PLL for use by peripheral clocks */
831#define TEGRA186_CLK_PLLP 516
832/** @deprecated */
833#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
834/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
835#define TEGRA186_CLK_PLLD 518
836/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
837#define TEGRA186_CLK_PLLD2 519
838/**
839 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
840 * @details Note that this clock only controls the VCO output, before
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
842 * information.
843 */
844#define TEGRA186_CLK_PLLREFE_VCO 520
845/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
846#define TEGRA186_CLK_PLLC2 521
847/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
848#define TEGRA186_CLK_PLLC3 522
849/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
850#define TEGRA186_CLK_PLLDP 523
851/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
852#define TEGRA186_CLK_PLLC4_VCO 524
853/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
854#define TEGRA186_CLK_PLLA1 525
855/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
856#define TEGRA186_CLK_PLLNVCSI 526
857/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
858#define TEGRA186_CLK_PLLDISPHUB 527
859/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
860#define TEGRA186_CLK_PLLD3 528
861/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
862#define TEGRA186_CLK_PLLBPMPCAM 531
863/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
864#define TEGRA186_CLK_PLLAON 532
865/** Fixed frequency 960MHz PLL for USB and EAVB */
866#define TEGRA186_CLK_PLLU 533
867/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
868#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
869/** @brief NAFLL clock source for AXI_CBB */
870#define TEGRA186_CLK_NAFLL_AXI_CBB 564
871/** @brief NAFLL clock source for BPMP */
872#define TEGRA186_CLK_NAFLL_BPMP 565
873/** @brief NAFLL clock source for ISP */
874#define TEGRA186_CLK_NAFLL_ISP 566
875/** @brief NAFLL clock source for NVDEC */
876#define TEGRA186_CLK_NAFLL_NVDEC 567
877/** @brief NAFLL clock source for NVENC */
878#define TEGRA186_CLK_NAFLL_NVENC 568
879/** @brief NAFLL clock source for NVJPG */
880#define TEGRA186_CLK_NAFLL_NVJPG 569
881/** @brief NAFLL clock source for SCE */
882#define TEGRA186_CLK_NAFLL_SCE 570
883/** @brief NAFLL clock source for SE */
884#define TEGRA186_CLK_NAFLL_SE 571
885/** @brief NAFLL clock source for TSEC */
886#define TEGRA186_CLK_NAFLL_TSEC 572
887/** @brief NAFLL clock source for TSECB */
888#define TEGRA186_CLK_NAFLL_TSECB 573
889/** @brief NAFLL clock source for VI */
890#define TEGRA186_CLK_NAFLL_VI 574
891/** @brief NAFLL clock source for VIC */
892#define TEGRA186_CLK_NAFLL_VIC 575
893/** @brief NAFLL clock source for DISP */
894#define TEGRA186_CLK_NAFLL_DISP 576
895/** @brief NAFLL clock source for GPU */
896#define TEGRA186_CLK_NAFLL_GPU 577
897/** @brief NAFLL clock source for M-CPU cluster */
898#define TEGRA186_CLK_NAFLL_MCPU 578
899/** @brief NAFLL clock source for B-CPU cluster */
900#define TEGRA186_CLK_NAFLL_BCPU 579
901/** @brief input from Tegra's CLK_32K_IN pad */
902#define TEGRA186_CLK_CLK_32K 608
903/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
904#define TEGRA186_CLK_CLK_M 609
905/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
906#define TEGRA186_CLK_PLL_REF 610
907/** @brief input from Tegra's XTAL_IN */
908#define TEGRA186_CLK_OSC 612
909/** @brief clock recovered from EAVB input */
910#define TEGRA186_CLK_EQOS_RX_INPUT 613
911/** @brief clock recovered from DTV input */
912#define TEGRA186_CLK_DTV_INPUT 614
913/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
914#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
915/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
916#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
917/** @brief clock recovered from I2S1 input */
918#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
919/** @brief clock recovered from I2S2 input */
920#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
921/** @brief clock recovered from I2S3 input */
922#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
923/** @brief clock recovered from I2S4 input */
924#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
925/** @brief clock recovered from I2S5 input */
926#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
927/** @brief clock recovered from I2S6 input */
928#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
929/** @brief clock recovered from SPDIFIN input */
930#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
931
932/**
933 * @brief subject to change
934 * @details maximum clock identifier value plus one.
935 */
936#define TEGRA186_CLK_CLK_MAX 624
937
938/** @} */
939
940#endif
941