1#ifndef _PPC_KERNEL_MPC8349_PCI_H 2#define _PPC_KERNEL_MPC8349_PCI_H 3 4 5#define M8265_PCIBR0 0x101ac 6#define M8265_PCIBR1 0x101b0 7#define M8265_PCIMSK0 0x101c4 8#define M8265_PCIMSK1 0x101c8 9 10/* Bit definitions for PCIBR registers */ 11 12#define PCIBR_ENABLE 0x00000001 13 14/* Bit definitions for PCIMSK registers */ 15 16#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ 17#define PCIMSK_64KB 0xFFFF0000 18#define PCIMSK_128KB 0xFFFE0000 19#define PCIMSK_256KB 0xFFFC0000 20#define PCIMSK_512KB 0xFFF80000 21#define PCIMSK_1MB 0xFFF00000 22#define PCIMSK_2MB 0xFFE00000 23#define PCIMSK_4MB 0xFFC00000 24#define PCIMSK_8MB 0xFF800000 25#define PCIMSK_16MB 0xFF000000 26#define PCIMSK_32MB 0xFE000000 27#define PCIMSK_64MB 0xFC000000 28#define PCIMSK_128MB 0xF8000000 29#define PCIMSK_256MB 0xF0000000 30#define PCIMSK_512MB 0xE0000000 31#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ 32 33 34#define M826X_SCCR_PCI_MODE_EN 0x100 35 36 37/* 38 * Outbound ATU registers (3 sets). These registers control how 60x bus 39 * (local) addresses are translated to PCI addresses when the MPC826x is 40 * a PCI bus master (initiator). 41 */ 42 43#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ 44#define POTAR_REG1 0x10818 45#define POTAR_REG2 0x10830 46 47#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ 48#define POBAR_REG1 0x10820 49#define POBAR_REG2 0x10838 50 51#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ 52#define POCMR_REG1 0x10828 53#define POCMR_REG2 0x10840 54 55/* Bit definitions for POMCR registers */ 56 57#define POCMR_MASK_4KB 0x000FFFFF 58#define POCMR_MASK_8KB 0x000FFFFE 59#define POCMR_MASK_16KB 0x000FFFFC 60#define POCMR_MASK_32KB 0x000FFFF8 61#define POCMR_MASK_64KB 0x000FFFF0 62#define POCMR_MASK_128KB 0x000FFFE0 63#define POCMR_MASK_256KB 0x000FFFC0 64#define POCMR_MASK_512KB 0x000FFF80 65#define POCMR_MASK_1MB 0x000FFF00 66#define POCMR_MASK_2MB 0x000FFE00 67#define POCMR_MASK_4MB 0x000FFC00 68#define POCMR_MASK_8MB 0x000FF800 69#define POCMR_MASK_16MB 0x000FF000 70#define POCMR_MASK_32MB 0x000FE000 71#define POCMR_MASK_64MB 0x000FC000 72#define POCMR_MASK_128MB 0x000F8000 73#define POCMR_MASK_256MB 0x000F0000 74#define POCMR_MASK_512MB 0x000E0000 75#define POCMR_MASK_1GB 0x000C0000 76 77#define POCMR_ENABLE 0x80000000 78#define POCMR_PCI_IO 0x40000000 79#define POCMR_PREFETCH_EN 0x20000000 80#define POCMR_PCI2 0x10000000 81 82/* Soft PCI reset */ 83 84#define PCI_GCR_REG 0x10880 85 86/* Bit definitions for PCI_GCR registers */ 87 88#define PCIGCR_PCI_BUS_EN 0x1 89 90/* 91 * Inbound ATU registers (2 sets). These registers control how PCI 92 * addresses are translated to 60x bus (local) addresses when the 93 * MPC826x is a PCI bus target. 94 */ 95 96#define PITAR_REG1 0x108D0 97#define PIBAR_REG1 0x108D8 98#define PICMR_REG1 0x108E0 99#define PITAR_REG0 0x108E8 100#define PIBAR_REG0 0x108F0 101#define PICMR_REG0 0x108F8 102 103/* Bit definitions for PCI Inbound Comparison Mask registers */ 104 105#define PICMR_MASK_4KB 0x000FFFFF 106#define PICMR_MASK_8KB 0x000FFFFE 107#define PICMR_MASK_16KB 0x000FFFFC 108#define PICMR_MASK_32KB 0x000FFFF8 109#define PICMR_MASK_64KB 0x000FFFF0 110#define PICMR_MASK_128KB 0x000FFFE0 111#define PICMR_MASK_256KB 0x000FFFC0 112#define PICMR_MASK_512KB 0x000FFF80 113#define PICMR_MASK_1MB 0x000FFF00 114#define PICMR_MASK_2MB 0x000FFE00 115#define PICMR_MASK_4MB 0x000FFC00 116#define PICMR_MASK_8MB 0x000FF800 117#define PICMR_MASK_16MB 0x000FF000 118#define PICMR_MASK_32MB 0x000FE000 119#define PICMR_MASK_64MB 0x000FC000 120#define PICMR_MASK_128MB 0x000F8000 121#define PICMR_MASK_256MB 0x000F0000 122#define PICMR_MASK_512MB 0x000E0000 123#define PICMR_MASK_1GB 0x000C0000 124 125#define PICMR_ENABLE 0x80000000 126#define PICMR_NO_SNOOP_EN 0x40000000 127#define PICMR_PREFETCH_EN 0x20000000 128 129/* PCI error Registers */ 130 131#define PCI_ERROR_STATUS_REG 0x10884 132#define PCI_ERROR_MASK_REG 0x10888 133#define PCI_ERROR_CONTROL_REG 0x1088C 134#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 135#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 136#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 137 138/* PCI error Register bit defines */ 139 140#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 141#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 142#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 143#define PCI_ERROR_PCI_NO_RSP 0x00000008 144#define PCI_ERROR_PCI_TAR_ABT 0x00000010 145#define PCI_ERROR_PCI_SERR 0x00000020 146#define PCI_ERROR_PCI_PERR_RD 0x00000040 147#define PCI_ERROR_PCI_PERR_WR 0x00000080 148#define PCI_ERROR_I2O_OFQO 0x00000100 149#define PCI_ERROR_I2O_IPQO 0x00000200 150#define PCI_ERROR_IRA 0x00000400 151#define PCI_ERROR_NMI 0x00000800 152#define PCI_ERROR_I2O_DBMC 0x00001000 153 154/* 155 * Register pair used to generate configuration cycles on the PCI bus 156 * and access the MPC826x's own PCI configuration registers. 157 */ 158 159#define PCI_CFG_ADDR_REG 0x10900 160#define PCI_CFG_DATA_REG 0x10904 161 162/* Bus parking decides where the bus control sits when idle */ 163/* If modifying memory controllers for PCI park on the core */ 164 165#define PPC_ACR_BUS_PARK_CORE 0x6 166#define PPC_ACR_BUS_PARK_PCI 0x3 167 168#endif /* _PPC_KERNEL_M8260_PCI_H */ 169