1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 */
5
6#ifndef _ASM_CONFIG_H_
7#define _ASM_CONFIG_H_
8
9#ifdef CONFIG_MPC85xx
10#include <asm/config_mpc85xx.h>
11#endif
12
13#ifndef HWCONFIG_BUFFER_SIZE
14  #define HWCONFIG_BUFFER_SIZE 256
15#endif
16
17#ifndef CFG_MAX_MEM_MAPPED
18#if	defined(CONFIG_E500)		|| \
19	defined(CONFIG_MPC86xx)		|| \
20	defined(CONFIG_E300)
21#define CFG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
22#else
23#define CFG_MAX_MEM_MAPPED	(256 << 20)
24#endif
25#endif
26
27/*
28 * Provide a default boot page translation virtual address that lines up with
29 * Freescale's default e500 reset page.
30 */
31#if (defined(CONFIG_E500) && defined(CONFIG_MP))
32#define BPTR_VIRT_ADDR	0xfffff000
33#endif
34
35/* The TSEC driver uses the PHYLIB infrastructure */
36#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
37#include <config_phylib_all_drivers.h>
38#endif /* TSEC_ENET */
39
40/* The FMAN driver uses the PHYLIB infrastructure */
41
42#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
43/*
44 * TODO: Convert this to a clock driver exists that can give us the UART
45 * clock here.
46 */
47#define CFG_SYS_NS16550_CLK		get_serial_clock()
48#endif
49
50#endif /* _ASM_CONFIG_H_ */
51