1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de 5 * 6 * Copyright 2009 Freescale Semiconductor, Inc. 7 */ 8 9#include "config.h" 10 11OUTPUT_ARCH(powerpc) 12 13SECTIONS 14{ 15/* Optional boot sector */ 16#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) 17 .bootsect IMAGE_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : { 18 KEEP(*(.bootsect)) 19 . = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512; 20 } 21#endif 22 23 . = IMAGE_TEXT_BASE; 24 .text : { 25/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ 26#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) 27 KEEP(*(.bootpg)) 28#endif 29 *(.text*) 30 } 31 _etext = .; 32 33 .reloc : { 34 _GOT2_TABLE_ = .; 35 KEEP(*(.got2)) 36 KEEP(*(.got)) 37 _FIXUP_TABLE_ = .; 38 KEEP(*(.fixup)) 39 } 40 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 41 __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 42 43 . = ALIGN(8); 44 .data : { 45 *(.rodata*) 46 *(.data*) 47 *(.sdata*) 48 } 49 _edata = .; 50 51 . = ALIGN(4); 52 __u_boot_list : { 53 KEEP(*(SORT(__u_boot_list*))); 54 } 55 56 . = .; 57 __start___ex_table = .; 58 __ex_table : { *(__ex_table) } 59 __stop___ex_table = .; 60 61 . = ALIGN(4); 62 __init_begin = .; 63 __init_end = .; 64 _end = .; 65 66#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) 67#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) 68 mmc_u_boot_offs = .; 69#endif 70#endif 71 72#ifdef CONFIG_SPL_SKIP_RELOCATE 73 . = ALIGN(4); 74 __bss_start = .; 75 .bss : { 76 *(.sbss*) 77 *(.bss*) 78 } 79 . = ALIGN(4); 80 __bss_end = .; 81#endif 82 83/* For nor and nand is needed the SPL with section .resetvec */ 84#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) 85#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ 86#ifndef BOOT_PAGE_OFFSET 87#define BOOT_PAGE_OFFSET 0x1000 88#endif 89 .bootpg IMAGE_TEXT_BASE + BOOT_PAGE_OFFSET : 90 { 91 arch/powerpc/cpu/mpc85xx/start.o (.bootpg) 92 } 93#ifndef RESET_VECTOR_OFFSET 94#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ 95#endif 96#elif defined(CONFIG_FSL_ELBC) 97#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ 98#else 99#error unknown NAND controller 100#endif 101 .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { 102 KEEP(*(.resetvec)) 103 } = 0xffff 104#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) 105 mmc_u_boot_offs = .; 106#endif 107#endif 108 109#ifndef CONFIG_SPL_SKIP_RELOCATE 110 /* 111 * Make sure that the bss segment isn't linked at 0x0, otherwise its 112 * address won't be updated during relocation fixups. 113 */ 114 . |= 0x10; 115 116 . = ALIGN(4); 117 __bss_start = .; 118 .bss : { 119 *(.sbss*) 120 *(.bss*) 121 } 122 . = ALIGN(4); 123 __bss_end = .; 124#endif 125} 126