1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 */
5
6#include <common.h>
7#include <asm/fsl_serdes.h>
8#include <asm/processor.h>
9#include <asm/io.h>
10
11
12static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
13	[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
14	[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
15	[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
16	[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
17	[0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
18	[0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
19	[0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
20	[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
21	[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
22	[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
23	[0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
24	[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
25	[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
26	[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
27		  SGMII_2500_FM1_DTSEC1},
28	[0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
29	[0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
30		  SGMII_2500_FM1_DTSEC1},
31	[0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
32	[0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
33};
34
35enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
36{
37	return serdes_cfg_tbl[cfg][lane];
38}
39
40int is_serdes_prtcl_valid(int serdes, u32 prtcl)
41{
42	int i;
43
44	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
45		return 0;
46
47	for (i = 0; i < SRDS_MAX_LANES; i++) {
48		if (serdes_cfg_tbl[prtcl][i] != NONE)
49			return 1;
50	}
51
52	return 0;
53}
54