1menu "LCRR - Clock Ratio Register register"
2
3if !ARCH_MPC831X && !ARCH_MPC832X
4
5choice
6	prompt "DLL bypass"
7
8config LCRR_DBYP_UNSET
9	bool "Don't set value"
10
11config LCRR_DBYP_PLL_ENABLED
12	bool "PLL enabled"
13
14config LCRR_DBYP_PLL_BYPASSED
15	bool "PLL bypassed"
16
17endchoice
18
19endif
20
21if ARCH_MPC834X || ARCH_MPC8360
22
23choice
24	prompt "Additional delay cycles for SDRAM control signals"
25
26config LCRR_BUFCMDC_UNSET
27	bool "Don't set value"
28
29config LCRR_BUFCMDC_4
30	bool "4"
31
32config LCRR_BUFCMDC_1
33	bool "1"
34
35config LCRR_BUFCMDC_2
36	bool "2"
37
38config LCRR_BUFCMDC_3
39	bool "3"
40
41endchoice
42
43choice
44	prompt "Extended CAS latency"
45
46config LCRR_ECL_UNSET
47	bool "Don't set value"
48
49config LCRR_ECL_4
50	bool "4"
51
52config LCRR_ECL_5
53	bool "5"
54
55config LCRR_ECL_6
56	bool "6"
57
58config LCRR_ECL_7
59	bool "7"
60
61endchoice
62
63endif # ARCH_MPC834X || ARCH_MPC8360
64
65if !ARCH_MPC8308
66
67choice
68	prompt "External address delay cycles"
69
70config LCRR_EADC_UNSET
71	bool "Don't set value"
72
73config LCRR_EADC_4
74	bool "4"
75
76config LCRR_EADC_1
77	bool "1"
78
79config LCRR_EADC_2
80	bool "2"
81
82config LCRR_EADC_3
83	bool "3"
84
85endchoice
86
87endif # !ARCH_MPC8308
88
89choice
90	prompt "System clock divider"
91
92config LCRR_CLKDIV_UNSET
93	bool "Don't set value"
94
95config LCRR_CLKDIV_2
96	bool "2"
97
98config LCRR_CLKDIV_4
99	bool "4"
100
101config LCRR_CLKDIV_8
102	bool "8"
103
104endchoice
105
106config LCRR_DBYP
107	hex
108	default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
109	default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
110
111config LCRR_BUFCMDC
112	hex
113	default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
114	default 0x10000000 if LCRR_BUFCMDC_1
115	default 0x20000000 if LCRR_BUFCMDC_2
116	default 0x30000000 if LCRR_BUFCMDC_3
117
118config LCRR_ECL
119	hex
120	default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
121	default 0x1000000 if LCRR_ECL_5
122	default 0x2000000 if LCRR_ECL_6
123	default 0x3000000 if LCRR_ECL_7
124
125config LCRR_EADC
126	hex
127	default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
128	default 0x10000 if LCRR_EADC_1
129	default 0x20000 if LCRR_EADC_2
130	default 0x30000 if LCRR_EADC_3
131
132config LCRR_CLKDIV
133	hex
134	default 0x0 if LCRR_CLKDIV_UNSET
135	default 0x2 if LCRR_CLKDIV_2
136	default 0x4 if LCRR_CLKDIV_4
137	default 0x8 if LCRR_CLKDIV_8
138
139endmenu
140