1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_MT8183_H 8#define _DT_BINDINGS_CLK_MT8183_H 9 10/* APMIXED */ 11#define CLK_APMIXED_ARMPLL_LL 0 12#define CLK_APMIXED_ARMPLL_L 1 13#define CLK_APMIXED_CCIPLL 2 14#define CLK_APMIXED_MAINPLL 3 15#define CLK_APMIXED_UNIV2PLL 4 16#define CLK_APMIXED_MSDCPLL 5 17#define CLK_APMIXED_MMPLL 6 18#define CLK_APMIXED_MFGPLL 7 19#define CLK_APMIXED_TVDPLL 8 20#define CLK_APMIXED_APLL1 9 21#define CLK_APMIXED_APLL2 10 22#define CLK_APMIXED_SSUSB_26M 11 23#define CLK_APMIXED_APPLL_26M 12 24#define CLK_APMIXED_MIPIC0_26M 13 25#define CLK_APMIXED_MDPLLGP_26M 14 26#define CLK_APMIXED_MMSYS_26M 15 27#define CLK_APMIXED_UFS_26M 16 28#define CLK_APMIXED_MIPIC1_26M 17 29#define CLK_APMIXED_MEMPLL_26M 18 30#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 31#define CLK_APMIXED_MIPID0_26M 20 32#define CLK_APMIXED_MIPID1_26M 21 33#define CLK_APMIXED_NR_CLK 22 34 35/* TOPCKGEN */ 36#define CLK_TOP_CLK26M 0 37#define CLK_TOP_ULPOSC 1 38#define CLK_TOP_UNIVP_192M 2 39#define CLK_TOP_CLK13M 3 40#define CLK_TOP_F26M_CK_D2 4 41#define CLK_TOP_SYSPLL_CK 5 42#define CLK_TOP_SYSPLL_D2 6 43#define CLK_TOP_SYSPLL_D3 7 44#define CLK_TOP_SYSPLL_D5 8 45#define CLK_TOP_SYSPLL_D7 9 46#define CLK_TOP_SYSPLL_D2_D2 10 47#define CLK_TOP_SYSPLL_D2_D4 11 48#define CLK_TOP_SYSPLL_D2_D8 12 49#define CLK_TOP_SYSPLL_D2_D16 13 50#define CLK_TOP_SYSPLL_D3_D2 14 51#define CLK_TOP_SYSPLL_D3_D4 15 52#define CLK_TOP_SYSPLL_D3_D8 16 53#define CLK_TOP_SYSPLL_D5_D2 17 54#define CLK_TOP_SYSPLL_D5_D4 18 55#define CLK_TOP_SYSPLL_D7_D2 19 56#define CLK_TOP_SYSPLL_D7_D4 20 57#define CLK_TOP_UNIVPLL_CK 21 58#define CLK_TOP_UNIVPLL_D2 22 59#define CLK_TOP_UNIVPLL_D3 23 60#define CLK_TOP_UNIVPLL_D5 24 61#define CLK_TOP_UNIVPLL_D7 25 62#define CLK_TOP_UNIVPLL_D2_D2 26 63#define CLK_TOP_UNIVPLL_D2_D4 27 64#define CLK_TOP_UNIVPLL_D2_D8 28 65#define CLK_TOP_UNIVPLL_D3_D2 29 66#define CLK_TOP_UNIVPLL_D3_D4 30 67#define CLK_TOP_UNIVPLL_D3_D8 31 68#define CLK_TOP_UNIVPLL_D5_D2 32 69#define CLK_TOP_UNIVPLL_D5_D4 33 70#define CLK_TOP_UNIVPLL_D5_D8 34 71#define CLK_TOP_UNIVP_192M_CK 35 72#define CLK_TOP_UNIVP_192M_D2 36 73#define CLK_TOP_UNIVP_192M_D4 37 74#define CLK_TOP_UNIVP_192M_D8 38 75#define CLK_TOP_UNIVP_192M_D16 39 76#define CLK_TOP_UNIVP_192M_D32 40 77#define CLK_TOP_APLL1_CK 41 78#define CLK_TOP_APLL1_D2 42 79#define CLK_TOP_APLL1_D4 43 80#define CLK_TOP_APLL1_D8 44 81#define CLK_TOP_APLL2_CK 45 82#define CLK_TOP_APLL2_D2 46 83#define CLK_TOP_APLL2_D4 47 84#define CLK_TOP_APLL2_D8 48 85#define CLK_TOP_TVDPLL_CK 49 86#define CLK_TOP_TVDPLL_D2 50 87#define CLK_TOP_TVDPLL_D4 51 88#define CLK_TOP_TVDPLL_D8 52 89#define CLK_TOP_TVDPLL_D16 53 90#define CLK_TOP_MMPLL_CK 54 91#define CLK_TOP_MMPLL_D4 55 92#define CLK_TOP_MMPLL_D4_D2 56 93#define CLK_TOP_MMPLL_D4_D4 57 94#define CLK_TOP_MMPLL_D5 58 95#define CLK_TOP_MMPLL_D5_D2 59 96#define CLK_TOP_MMPLL_D5_D4 60 97#define CLK_TOP_MMPLL_D6 61 98#define CLK_TOP_MMPLL_D7 62 99#define CLK_TOP_MFGPLL_CK 63 100#define CLK_TOP_MSDCPLL_CK 64 101#define CLK_TOP_MSDCPLL_D2 65 102#define CLK_TOP_MSDCPLL_D4 66 103#define CLK_TOP_MSDCPLL_D8 67 104#define CLK_TOP_MSDCPLL_D16 68 105#define CLK_TOP_AD_OSC_CK 69 106#define CLK_TOP_OSC_D2 70 107#define CLK_TOP_OSC_D4 71 108#define CLK_TOP_OSC_D8 72 109#define CLK_TOP_OSC_D16 73 110#define CLK_TOP_UNIVPLL 74 111#define CLK_TOP_UNIVPLL_D3_D16 75 112#define CLK_TOP_APLL12_DIV0 76 113#define CLK_TOP_APLL12_DIV1 77 114#define CLK_TOP_APLL12_DIV2 78 115#define CLK_TOP_APLL12_DIV3 79 116#define CLK_TOP_APLL12_DIV4 80 117#define CLK_TOP_APLL12_DIVB 81 118#define CLK_TOP_ARMPLL_DIV_PLL1 82 119#define CLK_TOP_ARMPLL_DIV_PLL2 83 120#define CLK_TOP_MUX_AXI 84 121#define CLK_TOP_MUX_MM 85 122#define CLK_TOP_MUX_IMG 86 123#define CLK_TOP_MUX_CAM 87 124#define CLK_TOP_MUX_DSP 88 125#define CLK_TOP_MUX_DSP1 89 126#define CLK_TOP_MUX_DSP2 90 127#define CLK_TOP_MUX_IPU_IF 91 128#define CLK_TOP_MUX_MFG 92 129#define CLK_TOP_MUX_F52M_MFG 93 130#define CLK_TOP_MUX_CAMTG 94 131#define CLK_TOP_MUX_CAMTG2 95 132#define CLK_TOP_MUX_CAMTG3 96 133#define CLK_TOP_MUX_CAMTG4 97 134#define CLK_TOP_MUX_UART 98 135#define CLK_TOP_MUX_SPI 99 136#define CLK_TOP_MUX_MSDC50_0_HCLK 100 137#define CLK_TOP_MUX_MSDC50_0 101 138#define CLK_TOP_MUX_MSDC30_1 102 139#define CLK_TOP_MUX_MSDC30_2 103 140#define CLK_TOP_MUX_AUDIO 104 141#define CLK_TOP_MUX_AUD_INTBUS 105 142#define CLK_TOP_MUX_PMICSPI 106 143#define CLK_TOP_MUX_FPWRAP_ULPOSC 107 144#define CLK_TOP_MUX_ATB 108 145#define CLK_TOP_MUX_SSPM 109 146#define CLK_TOP_MUX_DPI0 110 147#define CLK_TOP_MUX_SCAM 111 148#define CLK_TOP_MUX_DISP_PWM 112 149#define CLK_TOP_MUX_USB_TOP 113 150#define CLK_TOP_MUX_SSUSB_TOP_XHCI 114 151#define CLK_TOP_MUX_SPM 115 152#define CLK_TOP_MUX_I2C 116 153#define CLK_TOP_MUX_SCP 117 154#define CLK_TOP_MUX_SENINF 118 155#define CLK_TOP_MUX_DXCC 119 156#define CLK_TOP_MUX_AUD_ENG1 120 157#define CLK_TOP_MUX_AUD_ENG2 121 158#define CLK_TOP_MUX_FAES_UFSFDE 122 159#define CLK_TOP_MUX_FUFS 123 160#define CLK_TOP_MUX_AUD_1 124 161#define CLK_TOP_MUX_AUD_2 125 162#define CLK_TOP_MUX_APLL_I2S0 126 163#define CLK_TOP_MUX_APLL_I2S1 127 164#define CLK_TOP_MUX_APLL_I2S2 128 165#define CLK_TOP_MUX_APLL_I2S3 129 166#define CLK_TOP_MUX_APLL_I2S4 130 167#define CLK_TOP_MUX_APLL_I2S5 131 168#define CLK_TOP_NR_CLK 132 169 170/* INFRACFG_AO */ 171#define CLK_INFRA_PMIC_TMR 0 172#define CLK_INFRA_PMIC_AP 1 173#define CLK_INFRA_PMIC_MD 2 174#define CLK_INFRA_PMIC_CONN 3 175#define CLK_INFRA_SCPSYS 4 176#define CLK_INFRA_SEJ 5 177#define CLK_INFRA_APXGPT 6 178#define CLK_INFRA_ICUSB 7 179#define CLK_INFRA_GCE 8 180#define CLK_INFRA_THERM 9 181#define CLK_INFRA_I2C0 10 182#define CLK_INFRA_I2C1 11 183#define CLK_INFRA_I2C2 12 184#define CLK_INFRA_I2C3 13 185#define CLK_INFRA_PWM_HCLK 14 186#define CLK_INFRA_PWM1 15 187#define CLK_INFRA_PWM2 16 188#define CLK_INFRA_PWM3 17 189#define CLK_INFRA_PWM4 18 190#define CLK_INFRA_PWM 19 191#define CLK_INFRA_UART0 20 192#define CLK_INFRA_UART1 21 193#define CLK_INFRA_UART2 22 194#define CLK_INFRA_UART3 23 195#define CLK_INFRA_GCE_26M 24 196#define CLK_INFRA_CQ_DMA_FPC 25 197#define CLK_INFRA_BTIF 26 198#define CLK_INFRA_SPI0 27 199#define CLK_INFRA_MSDC0 28 200#define CLK_INFRA_MSDC1 29 201#define CLK_INFRA_MSDC2 30 202#define CLK_INFRA_MSDC0_SCK 31 203#define CLK_INFRA_DVFSRC 32 204#define CLK_INFRA_GCPU 33 205#define CLK_INFRA_TRNG 34 206#define CLK_INFRA_AUXADC 35 207#define CLK_INFRA_CPUM 36 208#define CLK_INFRA_CCIF1_AP 37 209#define CLK_INFRA_CCIF1_MD 38 210#define CLK_INFRA_AUXADC_MD 39 211#define CLK_INFRA_MSDC1_SCK 40 212#define CLK_INFRA_MSDC2_SCK 41 213#define CLK_INFRA_AP_DMA 42 214#define CLK_INFRA_XIU 43 215#define CLK_INFRA_DEVICE_APC 44 216#define CLK_INFRA_CCIF_AP 45 217#define CLK_INFRA_DEBUGSYS 46 218#define CLK_INFRA_AUDIO 47 219#define CLK_INFRA_CCIF_MD 48 220#define CLK_INFRA_DXCC_SEC_CORE 49 221#define CLK_INFRA_DXCC_AO 50 222#define CLK_INFRA_DRAMC_F26M 51 223#define CLK_INFRA_IRTX 52 224#define CLK_INFRA_DISP_PWM 53 225#define CLK_INFRA_CLDMA_BCLK 54 226#define CLK_INFRA_AUDIO_26M_BCLK 55 227#define CLK_INFRA_SPI1 56 228#define CLK_INFRA_I2C4 57 229#define CLK_INFRA_MODEM_TEMP_SHARE 58 230#define CLK_INFRA_SPI2 59 231#define CLK_INFRA_SPI3 60 232#define CLK_INFRA_UNIPRO_SCK 61 233#define CLK_INFRA_UNIPRO_TICK 62 234#define CLK_INFRA_UFS_MP_SAP_BCLK 63 235#define CLK_INFRA_MD32_BCLK 64 236#define CLK_INFRA_SSPM 65 237#define CLK_INFRA_UNIPRO_MBIST 66 238#define CLK_INFRA_SSPM_BUS_HCLK 67 239#define CLK_INFRA_I2C5 68 240#define CLK_INFRA_I2C5_ARBITER 69 241#define CLK_INFRA_I2C5_IMM 70 242#define CLK_INFRA_I2C1_ARBITER 71 243#define CLK_INFRA_I2C1_IMM 72 244#define CLK_INFRA_I2C2_ARBITER 73 245#define CLK_INFRA_I2C2_IMM 74 246#define CLK_INFRA_SPI4 75 247#define CLK_INFRA_SPI5 76 248#define CLK_INFRA_CQ_DMA 77 249#define CLK_INFRA_UFS 78 250#define CLK_INFRA_AES_UFSFDE 79 251#define CLK_INFRA_UFS_TICK 80 252#define CLK_INFRA_MSDC0_SELF 81 253#define CLK_INFRA_MSDC1_SELF 82 254#define CLK_INFRA_MSDC2_SELF 83 255#define CLK_INFRA_SSPM_26M_SELF 84 256#define CLK_INFRA_SSPM_32K_SELF 85 257#define CLK_INFRA_UFS_AXI 86 258#define CLK_INFRA_I2C6 87 259#define CLK_INFRA_AP_MSDC0 88 260#define CLK_INFRA_MD_MSDC0 89 261#define CLK_INFRA_USB 90 262#define CLK_INFRA_DEVMPU_BCLK 91 263#define CLK_INFRA_CCIF2_AP 92 264#define CLK_INFRA_CCIF2_MD 93 265#define CLK_INFRA_CCIF3_AP 94 266#define CLK_INFRA_CCIF3_MD 95 267#define CLK_INFRA_SEJ_F13M 96 268#define CLK_INFRA_AES_BCLK 97 269#define CLK_INFRA_I2C7 98 270#define CLK_INFRA_I2C8 99 271#define CLK_INFRA_FBIST2FPC 100 272#define CLK_INFRA_NR_CLK 101 273 274/* MMSYS_CONFIG */ 275#define CLK_MM_SMI_COMMON 0 276#define CLK_MM_SMI_LARB0 1 277#define CLK_MM_SMI_LARB1 2 278#define CLK_MM_GALS_COMM0 3 279#define CLK_MM_GALS_COMM1 4 280#define CLK_MM_GALS_CCU2MM 5 281#define CLK_MM_GALS_IPU12MM 6 282#define CLK_MM_GALS_IMG2MM 7 283#define CLK_MM_GALS_CAM2MM 8 284#define CLK_MM_GALS_IPU2MM 9 285#define CLK_MM_MDP_DL_TXCK 10 286#define CLK_MM_IPU_DL_TXCK 11 287#define CLK_MM_MDP_RDMA0 12 288#define CLK_MM_MDP_RDMA1 13 289#define CLK_MM_MDP_RSZ0 14 290#define CLK_MM_MDP_RSZ1 15 291#define CLK_MM_MDP_TDSHP 16 292#define CLK_MM_MDP_WROT0 17 293#define CLK_MM_FAKE_ENG 18 294#define CLK_MM_DISP_OVL0 19 295#define CLK_MM_DISP_OVL0_2L 20 296#define CLK_MM_DISP_OVL1_2L 21 297#define CLK_MM_DISP_RDMA0 22 298#define CLK_MM_DISP_RDMA1 23 299#define CLK_MM_DISP_WDMA0 24 300#define CLK_MM_DISP_COLOR0 25 301#define CLK_MM_DISP_CCORR0 26 302#define CLK_MM_DISP_AAL0 27 303#define CLK_MM_DISP_GAMMA0 28 304#define CLK_MM_DISP_DITHER0 29 305#define CLK_MM_DISP_SPLIT 30 306#define CLK_MM_DSI0_MM 31 307#define CLK_MM_DSI0_IF 32 308#define CLK_MM_DPI_MM 33 309#define CLK_MM_DPI_IF 34 310#define CLK_MM_FAKE_ENG2 35 311#define CLK_MM_MDP_DL_RX 36 312#define CLK_MM_IPU_DL_RX 37 313#define CLK_MM_26M 38 314#define CLK_MM_MMSYS_R2Y 39 315#define CLK_MM_DISP_RSZ 40 316#define CLK_MM_MDP_WDMA0 41 317#define CLK_MM_MDP_AAL 42 318#define CLK_MM_MDP_CCORR 43 319#define CLK_MM_DBI_MM 44 320#define CLK_MM_DBI_IF 45 321#define CLK_MM_NR_CLK 46 322 323/* MCUCFG */ 324#define CLK_MCU_MP0_SEL 0 325#define CLK_MCU_MP2_SEL 1 326#define CLK_MCU_BUS_SEL 2 327#define CLK_MCU_NR_CLK 3 328 329#endif /* _DT_BINDINGS_CLK_MT8183_H */ 330