1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
4 *
5 */
6
7#ifndef __PIC32_REGS_H__
8#define __PIC32_REGS_H__
9
10#include <asm/io.h>
11
12/* System Configuration */
13#define PIC32_CFG_BASE		0x1f800000
14
15/* System config register offsets */
16#define CFGCON		0x0000
17#define DEVID		0x0020
18#define SYSKEY		0x0030
19#define PMD1		0x0040
20#define PMD7		0x00a0
21#define CFGEBIA		0x00c0
22#define CFGEBIC		0x00d0
23#define CFGPG		0x00e0
24#define CFGMPLL		0x0100
25
26/* Non Volatile Memory (NOR flash) */
27#define PIC32_NVM_BASE		(PIC32_CFG_BASE + 0x0600)
28/* Oscillator Configuration */
29#define PIC32_OSC_BASE		(PIC32_CFG_BASE + 0x1200)
30/* Peripheral Pin Select Input */
31#define PPS_IN_BASE		0x1f801400
32/* Peripheral Pin Select Output */
33#define PPS_OUT_BASE		0x1f801500
34/* Pin Config */
35#define PINCTRL_BASE		0x1f860000
36
37/* USB Core */
38#define PIC32_USB_CORE_BASE	0x1f8e3000
39#define PIC32_USB_CTRL_BASE	0x1f884000
40
41/* SPI1-SPI6 */
42#define PIC32_SPI1_BASE		0x1f821000
43
44/* Prefetch Module */
45#define PREFETCH_BASE		0x1f8e0000
46
47/* DDR2 Controller */
48#define PIC32_DDR2C_BASE	0x1f8e8000
49
50/* DDR2 PHY */
51#define PIC32_DDR2P_BASE	0x1f8e9100
52
53/* EBI */
54#define PIC32_EBI_BASE		0x1f8e1000
55
56/* SQI */
57#define PIC32_SQI_BASE		0x1f8e2000
58
59struct pic32_reg_atomic {
60	u32 raw;
61	u32 clr;
62	u32 set;
63	u32 inv;
64};
65
66#define _CLR_OFFSET	0x04
67#define _SET_OFFSET	0x08
68#define _INV_OFFSET	0x0c
69
70static inline void __iomem *pic32_get_syscfg_base(void)
71{
72	return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
73}
74
75/* Core */
76const char *get_core_name(void);
77
78#endif	/* __PIC32_REGS_H__ */
79