1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon pcsx. 7 */ 8 9#ifndef __CVMX_PCSX_DEFS_H__ 10#define __CVMX_PCSX_DEFS_H__ 11 12static inline u64 CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) 13{ 14 switch (cvmx_get_octeon_family()) { 15 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 16 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 17 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 18 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024; 19 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 20 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024; 21 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 22 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 23 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x4000ull) * 1024; 24 } 25 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024; 26} 27 28static inline u64 CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) 29{ 30 switch (cvmx_get_octeon_family()) { 31 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 32 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 33 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 34 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024; 35 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 36 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024; 37 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 38 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 39 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x4000ull) * 1024; 40 } 41 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024; 42} 43 44static inline u64 CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) 45{ 46 switch (cvmx_get_octeon_family()) { 47 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 48 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 49 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 50 return 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024; 51 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 52 return 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024; 53 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 54 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 55 return 0x00011800B0001018ull + ((offset) + (block_id) * 0x4000ull) * 1024; 56 } 57 return 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024; 58} 59 60static inline u64 CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) 61{ 62 switch (cvmx_get_octeon_family()) { 63 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 64 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 65 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 66 return 0x00011800B0001020ull + ((offset) + (block_id) * 0x20000ull) * 1024; 67 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 68 return 0x00011800B0001020ull + ((offset) + (block_id) * 0x20000ull) * 1024; 69 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 70 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 71 return 0x00011800B0001020ull + ((offset) + (block_id) * 0x4000ull) * 1024; 72 } 73 return 0x00011800B0001020ull + ((offset) + (block_id) * 0x20000ull) * 1024; 74} 75 76static inline u64 CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) 77{ 78 switch (cvmx_get_octeon_family()) { 79 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 80 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 81 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 82 return 0x00011800B0001088ull + ((offset) + (block_id) * 0x20000ull) * 1024; 83 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 84 return 0x00011800B0001088ull + ((offset) + (block_id) * 0x20000ull) * 1024; 85 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 86 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 87 return 0x00011800B0001088ull + ((offset) + (block_id) * 0x4000ull) * 1024; 88 } 89 return 0x00011800B0001088ull + ((offset) + (block_id) * 0x20000ull) * 1024; 90} 91 92static inline u64 CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) 93{ 94 switch (cvmx_get_octeon_family()) { 95 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 96 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 97 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 98 return 0x00011800B0001080ull + ((offset) + (block_id) * 0x20000ull) * 1024; 99 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 100 return 0x00011800B0001080ull + ((offset) + (block_id) * 0x20000ull) * 1024; 101 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 102 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 103 return 0x00011800B0001080ull + ((offset) + (block_id) * 0x4000ull) * 1024; 104 } 105 return 0x00011800B0001080ull + ((offset) + (block_id) * 0x20000ull) * 1024; 106} 107 108static inline u64 CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) 109{ 110 switch (cvmx_get_octeon_family()) { 111 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 112 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 113 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 114 return 0x00011800B0001040ull + ((offset) + (block_id) * 0x20000ull) * 1024; 115 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 116 return 0x00011800B0001040ull + ((offset) + (block_id) * 0x20000ull) * 1024; 117 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 118 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 119 return 0x00011800B0001040ull + ((offset) + (block_id) * 0x4000ull) * 1024; 120 } 121 return 0x00011800B0001040ull + ((offset) + (block_id) * 0x20000ull) * 1024; 122} 123 124static inline u64 CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) 125{ 126 switch (cvmx_get_octeon_family()) { 127 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 128 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 129 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 130 return 0x00011800B0001090ull + ((offset) + (block_id) * 0x20000ull) * 1024; 131 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 132 return 0x00011800B0001090ull + ((offset) + (block_id) * 0x20000ull) * 1024; 133 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 134 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 135 return 0x00011800B0001090ull + ((offset) + (block_id) * 0x4000ull) * 1024; 136 } 137 return 0x00011800B0001090ull + ((offset) + (block_id) * 0x20000ull) * 1024; 138} 139 140#define CVMX_PCSX_MAC_CRDT_CNTX_REG(offset, block_id) \ 141 (0x00011800B00010B0ull + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 142static inline u64 CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) 143{ 144 switch (cvmx_get_octeon_family()) { 145 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 146 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 147 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 148 return 0x00011800B0001078ull + ((offset) + (block_id) * 0x20000ull) * 1024; 149 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 150 return 0x00011800B0001078ull + ((offset) + (block_id) * 0x20000ull) * 1024; 151 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 152 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 153 return 0x00011800B0001078ull + ((offset) + (block_id) * 0x4000ull) * 1024; 154 } 155 return 0x00011800B0001078ull + ((offset) + (block_id) * 0x20000ull) * 1024; 156} 157 158static inline u64 CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) 159{ 160 switch (cvmx_get_octeon_family()) { 161 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 162 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 163 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 164 return 0x00011800B0001000ull + ((offset) + (block_id) * 0x20000ull) * 1024; 165 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 166 return 0x00011800B0001000ull + ((offset) + (block_id) * 0x20000ull) * 1024; 167 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 168 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 169 return 0x00011800B0001000ull + ((offset) + (block_id) * 0x4000ull) * 1024; 170 } 171 return 0x00011800B0001000ull + ((offset) + (block_id) * 0x20000ull) * 1024; 172} 173 174static inline u64 CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) 175{ 176 switch (cvmx_get_octeon_family()) { 177 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 178 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 179 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 180 return 0x00011800B0001008ull + ((offset) + (block_id) * 0x20000ull) * 1024; 181 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 182 return 0x00011800B0001008ull + ((offset) + (block_id) * 0x20000ull) * 1024; 183 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 184 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 185 return 0x00011800B0001008ull + ((offset) + (block_id) * 0x4000ull) * 1024; 186 } 187 return 0x00011800B0001008ull + ((offset) + (block_id) * 0x20000ull) * 1024; 188} 189 190static inline u64 CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) 191{ 192 switch (cvmx_get_octeon_family()) { 193 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 194 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 195 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 196 return 0x00011800B0001058ull + ((offset) + (block_id) * 0x20000ull) * 1024; 197 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 198 return 0x00011800B0001058ull + ((offset) + (block_id) * 0x20000ull) * 1024; 199 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 200 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 201 return 0x00011800B0001058ull + ((offset) + (block_id) * 0x4000ull) * 1024; 202 } 203 return 0x00011800B0001058ull + ((offset) + (block_id) * 0x20000ull) * 1024; 204} 205 206static inline u64 CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) 207{ 208 switch (cvmx_get_octeon_family()) { 209 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 210 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 211 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 212 return 0x00011800B0001050ull + ((offset) + (block_id) * 0x20000ull) * 1024; 213 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 214 return 0x00011800B0001050ull + ((offset) + (block_id) * 0x20000ull) * 1024; 215 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 216 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 217 return 0x00011800B0001050ull + ((offset) + (block_id) * 0x4000ull) * 1024; 218 } 219 return 0x00011800B0001050ull + ((offset) + (block_id) * 0x20000ull) * 1024; 220} 221 222#define CVMX_PCSX_SERDES_CRDT_CNTX_REG(offset, block_id) \ 223 (0x00011800B00010A0ull + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 224static inline u64 CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) 225{ 226 switch (cvmx_get_octeon_family()) { 227 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 228 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 229 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 230 return 0x00011800B0001068ull + ((offset) + (block_id) * 0x20000ull) * 1024; 231 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 232 return 0x00011800B0001068ull + ((offset) + (block_id) * 0x20000ull) * 1024; 233 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 234 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 235 return 0x00011800B0001068ull + ((offset) + (block_id) * 0x4000ull) * 1024; 236 } 237 return 0x00011800B0001068ull + ((offset) + (block_id) * 0x20000ull) * 1024; 238} 239 240static inline u64 CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) 241{ 242 switch (cvmx_get_octeon_family()) { 243 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 244 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 245 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 246 return 0x00011800B0001070ull + ((offset) + (block_id) * 0x20000ull) * 1024; 247 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 248 return 0x00011800B0001070ull + ((offset) + (block_id) * 0x20000ull) * 1024; 249 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 250 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 251 return 0x00011800B0001070ull + ((offset) + (block_id) * 0x4000ull) * 1024; 252 } 253 return 0x00011800B0001070ull + ((offset) + (block_id) * 0x20000ull) * 1024; 254} 255 256static inline u64 CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) 257{ 258 switch (cvmx_get_octeon_family()) { 259 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 260 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 261 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 262 return 0x00011800B0001060ull + ((offset) + (block_id) * 0x20000ull) * 1024; 263 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 264 return 0x00011800B0001060ull + ((offset) + (block_id) * 0x20000ull) * 1024; 265 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 266 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 267 return 0x00011800B0001060ull + ((offset) + (block_id) * 0x4000ull) * 1024; 268 } 269 return 0x00011800B0001060ull + ((offset) + (block_id) * 0x20000ull) * 1024; 270} 271 272static inline u64 CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) 273{ 274 switch (cvmx_get_octeon_family()) { 275 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 276 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 277 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 278 return 0x00011800B0001048ull + ((offset) + (block_id) * 0x20000ull) * 1024; 279 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 280 return 0x00011800B0001048ull + ((offset) + (block_id) * 0x20000ull) * 1024; 281 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 282 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 283 return 0x00011800B0001048ull + ((offset) + (block_id) * 0x4000ull) * 1024; 284 } 285 return 0x00011800B0001048ull + ((offset) + (block_id) * 0x20000ull) * 1024; 286} 287 288/** 289 * cvmx_pcs#_an#_adv_reg 290 * 291 * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification, 292 * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating 293 * that the chip cannot operate in the corresponding modes. 294 * 295 * Bit [4] RM_FLT is a don't care when the selected mode is SGMII. 296 * 297 * 298 * 299 * PCS_AN_ADV_REG = AN Advertisement Register4 300 */ 301union cvmx_pcsx_anx_adv_reg { 302 u64 u64; 303 struct cvmx_pcsx_anx_adv_reg_s { 304 u64 reserved_16_63 : 48; 305 u64 np : 1; 306 u64 reserved_14_14 : 1; 307 u64 rem_flt : 2; 308 u64 reserved_9_11 : 3; 309 u64 pause : 2; 310 u64 hfd : 1; 311 u64 fd : 1; 312 u64 reserved_0_4 : 5; 313 } s; 314 struct cvmx_pcsx_anx_adv_reg_s cn52xx; 315 struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; 316 struct cvmx_pcsx_anx_adv_reg_s cn56xx; 317 struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; 318 struct cvmx_pcsx_anx_adv_reg_s cn61xx; 319 struct cvmx_pcsx_anx_adv_reg_s cn63xx; 320 struct cvmx_pcsx_anx_adv_reg_s cn63xxp1; 321 struct cvmx_pcsx_anx_adv_reg_s cn66xx; 322 struct cvmx_pcsx_anx_adv_reg_s cn68xx; 323 struct cvmx_pcsx_anx_adv_reg_s cn68xxp1; 324 struct cvmx_pcsx_anx_adv_reg_s cn70xx; 325 struct cvmx_pcsx_anx_adv_reg_s cn70xxp1; 326 struct cvmx_pcsx_anx_adv_reg_s cnf71xx; 327}; 328 329typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t; 330 331/** 332 * cvmx_pcs#_an#_ext_st_reg 333 * 334 * as per IEEE802.3 Clause 22 335 * 336 */ 337union cvmx_pcsx_anx_ext_st_reg { 338 u64 u64; 339 struct cvmx_pcsx_anx_ext_st_reg_s { 340 u64 reserved_16_63 : 48; 341 u64 thou_xfd : 1; 342 u64 thou_xhd : 1; 343 u64 thou_tfd : 1; 344 u64 thou_thd : 1; 345 u64 reserved_0_11 : 12; 346 } s; 347 struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; 348 struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; 349 struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; 350 struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; 351 struct cvmx_pcsx_anx_ext_st_reg_s cn61xx; 352 struct cvmx_pcsx_anx_ext_st_reg_s cn63xx; 353 struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1; 354 struct cvmx_pcsx_anx_ext_st_reg_s cn66xx; 355 struct cvmx_pcsx_anx_ext_st_reg_s cn68xx; 356 struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1; 357 struct cvmx_pcsx_anx_ext_st_reg_cn70xx { 358 u64 reserved_16_63 : 48; 359 u64 thou_xfd : 1; 360 u64 thou_xhd : 1; 361 u64 thou_tfd : 1; 362 u64 thou_thd : 1; 363 u64 reserved_11_0 : 12; 364 } cn70xx; 365 struct cvmx_pcsx_anx_ext_st_reg_cn70xx cn70xxp1; 366 struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx; 367}; 368 369typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t; 370 371/** 372 * cvmx_pcs#_an#_lp_abil_reg 373 * 374 * as per IEEE802.3 Clause 37 375 * 376 */ 377union cvmx_pcsx_anx_lp_abil_reg { 378 u64 u64; 379 struct cvmx_pcsx_anx_lp_abil_reg_s { 380 u64 reserved_16_63 : 48; 381 u64 np : 1; 382 u64 ack : 1; 383 u64 rem_flt : 2; 384 u64 reserved_9_11 : 3; 385 u64 pause : 2; 386 u64 hfd : 1; 387 u64 fd : 1; 388 u64 reserved_0_4 : 5; 389 } s; 390 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; 391 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; 392 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; 393 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; 394 struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx; 395 struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx; 396 struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1; 397 struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx; 398 struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx; 399 struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1; 400 struct cvmx_pcsx_anx_lp_abil_reg_s cn70xx; 401 struct cvmx_pcsx_anx_lp_abil_reg_s cn70xxp1; 402 struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx; 403}; 404 405typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t; 406 407/** 408 * cvmx_pcs#_an#_results_reg 409 * 410 * NOTE: 411 * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1 412 * the an_results_reg is valid. 413 */ 414union cvmx_pcsx_anx_results_reg { 415 u64 u64; 416 struct cvmx_pcsx_anx_results_reg_s { 417 u64 reserved_7_63 : 57; 418 u64 pause : 2; 419 u64 spd : 2; 420 u64 an_cpt : 1; 421 u64 dup : 1; 422 u64 link_ok : 1; 423 } s; 424 struct cvmx_pcsx_anx_results_reg_s cn52xx; 425 struct cvmx_pcsx_anx_results_reg_s cn52xxp1; 426 struct cvmx_pcsx_anx_results_reg_s cn56xx; 427 struct cvmx_pcsx_anx_results_reg_s cn56xxp1; 428 struct cvmx_pcsx_anx_results_reg_s cn61xx; 429 struct cvmx_pcsx_anx_results_reg_s cn63xx; 430 struct cvmx_pcsx_anx_results_reg_s cn63xxp1; 431 struct cvmx_pcsx_anx_results_reg_s cn66xx; 432 struct cvmx_pcsx_anx_results_reg_s cn68xx; 433 struct cvmx_pcsx_anx_results_reg_s cn68xxp1; 434 struct cvmx_pcsx_anx_results_reg_s cn70xx; 435 struct cvmx_pcsx_anx_results_reg_s cn70xxp1; 436 struct cvmx_pcsx_anx_results_reg_s cnf71xx; 437}; 438 439typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t; 440 441/** 442 * cvmx_pcs#_int#_en_reg 443 * 444 * PCS Interrupt Enable Register 445 * 446 */ 447union cvmx_pcsx_intx_en_reg { 448 u64 u64; 449 struct cvmx_pcsx_intx_en_reg_s { 450 u64 reserved_13_63 : 51; 451 u64 dbg_sync_en : 1; 452 u64 dup : 1; 453 u64 sync_bad_en : 1; 454 u64 an_bad_en : 1; 455 u64 rxlock_en : 1; 456 u64 rxbad_en : 1; 457 u64 rxerr_en : 1; 458 u64 txbad_en : 1; 459 u64 txfifo_en : 1; 460 u64 txfifu_en : 1; 461 u64 an_err_en : 1; 462 u64 xmit_en : 1; 463 u64 lnkspd_en : 1; 464 } s; 465 struct cvmx_pcsx_intx_en_reg_cn52xx { 466 u64 reserved_12_63 : 52; 467 u64 dup : 1; 468 u64 sync_bad_en : 1; 469 u64 an_bad_en : 1; 470 u64 rxlock_en : 1; 471 u64 rxbad_en : 1; 472 u64 rxerr_en : 1; 473 u64 txbad_en : 1; 474 u64 txfifo_en : 1; 475 u64 txfifu_en : 1; 476 u64 an_err_en : 1; 477 u64 xmit_en : 1; 478 u64 lnkspd_en : 1; 479 } cn52xx; 480 struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1; 481 struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx; 482 struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1; 483 struct cvmx_pcsx_intx_en_reg_s cn61xx; 484 struct cvmx_pcsx_intx_en_reg_s cn63xx; 485 struct cvmx_pcsx_intx_en_reg_s cn63xxp1; 486 struct cvmx_pcsx_intx_en_reg_s cn66xx; 487 struct cvmx_pcsx_intx_en_reg_s cn68xx; 488 struct cvmx_pcsx_intx_en_reg_s cn68xxp1; 489 struct cvmx_pcsx_intx_en_reg_s cn70xx; 490 struct cvmx_pcsx_intx_en_reg_s cn70xxp1; 491 struct cvmx_pcsx_intx_en_reg_s cnf71xx; 492}; 493 494typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t; 495 496/** 497 * cvmx_pcs#_int#_reg 498 * 499 * PCS Interrupt Register 500 * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising 501 * DBG_SYNC interrupt fires when code group synchronization state machine makes a transition from 502 * SYNC_ACQUIRED_1 state to SYNC_ACQUIRED_2 state(See IEEE 802.3-2005 figure 37-9). It is an 503 * indication that a bad code group 504 * was received after code group synchronizaton was achieved. This interrupt should be disabled 505 * during normal link operation. 506 * Use it as a debug help feature only. 507 */ 508union cvmx_pcsx_intx_reg { 509 u64 u64; 510 struct cvmx_pcsx_intx_reg_s { 511 u64 reserved_13_63 : 51; 512 u64 dbg_sync : 1; 513 u64 dup : 1; 514 u64 sync_bad : 1; 515 u64 an_bad : 1; 516 u64 rxlock : 1; 517 u64 rxbad : 1; 518 u64 rxerr : 1; 519 u64 txbad : 1; 520 u64 txfifo : 1; 521 u64 txfifu : 1; 522 u64 an_err : 1; 523 u64 xmit : 1; 524 u64 lnkspd : 1; 525 } s; 526 struct cvmx_pcsx_intx_reg_cn52xx { 527 u64 reserved_12_63 : 52; 528 u64 dup : 1; 529 u64 sync_bad : 1; 530 u64 an_bad : 1; 531 u64 rxlock : 1; 532 u64 rxbad : 1; 533 u64 rxerr : 1; 534 u64 txbad : 1; 535 u64 txfifo : 1; 536 u64 txfifu : 1; 537 u64 an_err : 1; 538 u64 xmit : 1; 539 u64 lnkspd : 1; 540 } cn52xx; 541 struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1; 542 struct cvmx_pcsx_intx_reg_cn52xx cn56xx; 543 struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1; 544 struct cvmx_pcsx_intx_reg_s cn61xx; 545 struct cvmx_pcsx_intx_reg_s cn63xx; 546 struct cvmx_pcsx_intx_reg_s cn63xxp1; 547 struct cvmx_pcsx_intx_reg_s cn66xx; 548 struct cvmx_pcsx_intx_reg_s cn68xx; 549 struct cvmx_pcsx_intx_reg_s cn68xxp1; 550 struct cvmx_pcsx_intx_reg_s cn70xx; 551 struct cvmx_pcsx_intx_reg_s cn70xxp1; 552 struct cvmx_pcsx_intx_reg_s cnf71xx; 553}; 554 555typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t; 556 557/** 558 * cvmx_pcs#_link#_timer_count_reg 559 * 560 * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register 561 * 562 */ 563union cvmx_pcsx_linkx_timer_count_reg { 564 u64 u64; 565 struct cvmx_pcsx_linkx_timer_count_reg_s { 566 u64 reserved_16_63 : 48; 567 u64 count : 16; 568 } s; 569 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; 570 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; 571 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; 572 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; 573 struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx; 574 struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx; 575 struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1; 576 struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx; 577 struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx; 578 struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1; 579 struct cvmx_pcsx_linkx_timer_count_reg_s cn70xx; 580 struct cvmx_pcsx_linkx_timer_count_reg_s cn70xxp1; 581 struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx; 582}; 583 584typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t; 585 586/** 587 * cvmx_pcs#_log_anl#_reg 588 * 589 * PCS Logic Analyzer Register 590 * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is 591 * effective only when LA_EN=1 592 * For normal operation(sgmii or 1000Base-X), this bit must be 0. 593 * See pcsx.csr for xaui logic analyzer mode. 594 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 595 */ 596union cvmx_pcsx_log_anlx_reg { 597 u64 u64; 598 struct cvmx_pcsx_log_anlx_reg_s { 599 u64 reserved_4_63 : 60; 600 u64 lafifovfl : 1; 601 u64 la_en : 1; 602 u64 pkt_sz : 2; 603 } s; 604 struct cvmx_pcsx_log_anlx_reg_s cn52xx; 605 struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; 606 struct cvmx_pcsx_log_anlx_reg_s cn56xx; 607 struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; 608 struct cvmx_pcsx_log_anlx_reg_s cn61xx; 609 struct cvmx_pcsx_log_anlx_reg_s cn63xx; 610 struct cvmx_pcsx_log_anlx_reg_s cn63xxp1; 611 struct cvmx_pcsx_log_anlx_reg_s cn66xx; 612 struct cvmx_pcsx_log_anlx_reg_s cn68xx; 613 struct cvmx_pcsx_log_anlx_reg_s cn68xxp1; 614 struct cvmx_pcsx_log_anlx_reg_s cn70xx; 615 struct cvmx_pcsx_log_anlx_reg_s cn70xxp1; 616 struct cvmx_pcsx_log_anlx_reg_s cnf71xx; 617}; 618 619typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t; 620 621/** 622 * cvmx_pcs#_mac_crdt_cnt#_reg 623 * 624 * PCS MAC Credit Count 625 * 626 */ 627union cvmx_pcsx_mac_crdt_cntx_reg { 628 u64 u64; 629 struct cvmx_pcsx_mac_crdt_cntx_reg_s { 630 u64 reserved_5_63 : 59; 631 u64 cnt : 5; 632 } s; 633 struct cvmx_pcsx_mac_crdt_cntx_reg_s cn70xx; 634 struct cvmx_pcsx_mac_crdt_cntx_reg_s cn70xxp1; 635}; 636 637typedef union cvmx_pcsx_mac_crdt_cntx_reg cvmx_pcsx_mac_crdt_cntx_reg_t; 638 639/** 640 * cvmx_pcs#_misc#_ctl_reg 641 * 642 * SGMII Misc Control Register 643 * SGMII bit [12] is really a misnomer, it is a decode of pi_qlm_cfg pins to indicate SGMII or 644 * 1000Base-X modes. 645 * Note: MODE bit 646 * When MODE=1, 1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37. 647 * When MODE=0, SGMII mode is selected and the following note will apply. 648 * Repeat note from SGM_AN_ADV register 649 * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the 650 * MAC_PHY mode bit in misc_ctl_reg 651 * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit 652 * and [0] is always 1. 653 * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results. 654 */ 655union cvmx_pcsx_miscx_ctl_reg { 656 u64 u64; 657 struct cvmx_pcsx_miscx_ctl_reg_s { 658 u64 reserved_13_63 : 51; 659 u64 sgmii : 1; 660 u64 gmxeno : 1; 661 u64 loopbck2 : 1; 662 u64 mac_phy : 1; 663 u64 mode : 1; 664 u64 an_ovrd : 1; 665 u64 samp_pt : 7; 666 } s; 667 struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; 668 struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; 669 struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; 670 struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; 671 struct cvmx_pcsx_miscx_ctl_reg_s cn61xx; 672 struct cvmx_pcsx_miscx_ctl_reg_s cn63xx; 673 struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1; 674 struct cvmx_pcsx_miscx_ctl_reg_s cn66xx; 675 struct cvmx_pcsx_miscx_ctl_reg_s cn68xx; 676 struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1; 677 struct cvmx_pcsx_miscx_ctl_reg_cn70xx { 678 u64 reserved_12_63 : 52; 679 u64 gmxeno : 1; 680 u64 loopbck2 : 1; 681 u64 mac_phy : 1; 682 u64 mode : 1; 683 u64 an_ovrd : 1; 684 u64 samp_pt : 7; 685 } cn70xx; 686 struct cvmx_pcsx_miscx_ctl_reg_cn70xx cn70xxp1; 687 struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx; 688}; 689 690typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t; 691 692/** 693 * cvmx_pcs#_mr#_control_reg 694 * 695 * NOTE: 696 * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results 697 * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set, 698 * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values 699 * from the pcs_mr_ctrl reg. 700 */ 701union cvmx_pcsx_mrx_control_reg { 702 u64 u64; 703 struct cvmx_pcsx_mrx_control_reg_s { 704 u64 reserved_16_63 : 48; 705 u64 reset : 1; 706 u64 loopbck1 : 1; 707 u64 spdlsb : 1; 708 u64 an_en : 1; 709 u64 pwr_dn : 1; 710 u64 reserved_10_10 : 1; 711 u64 rst_an : 1; 712 u64 dup : 1; 713 u64 coltst : 1; 714 u64 spdmsb : 1; 715 u64 uni : 1; 716 u64 reserved_0_4 : 5; 717 } s; 718 struct cvmx_pcsx_mrx_control_reg_s cn52xx; 719 struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; 720 struct cvmx_pcsx_mrx_control_reg_s cn56xx; 721 struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; 722 struct cvmx_pcsx_mrx_control_reg_s cn61xx; 723 struct cvmx_pcsx_mrx_control_reg_s cn63xx; 724 struct cvmx_pcsx_mrx_control_reg_s cn63xxp1; 725 struct cvmx_pcsx_mrx_control_reg_s cn66xx; 726 struct cvmx_pcsx_mrx_control_reg_s cn68xx; 727 struct cvmx_pcsx_mrx_control_reg_s cn68xxp1; 728 struct cvmx_pcsx_mrx_control_reg_s cn70xx; 729 struct cvmx_pcsx_mrx_control_reg_s cn70xxp1; 730 struct cvmx_pcsx_mrx_control_reg_s cnf71xx; 731}; 732 733typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t; 734 735/** 736 * cvmx_pcs#_mr#_status_reg 737 * 738 * Bits [15:9] in the Status Register indicate ability to operate as per those signalling 739 * specification, 740 * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, 741 * indicating 742 * that the chip cannot operate in the corresponding modes. 743 * Bit [4] RM_FLT is a don't care when the selected mode is SGMII. 744 */ 745union cvmx_pcsx_mrx_status_reg { 746 u64 u64; 747 struct cvmx_pcsx_mrx_status_reg_s { 748 u64 reserved_16_63 : 48; 749 u64 hun_t4 : 1; 750 u64 hun_xfd : 1; 751 u64 hun_xhd : 1; 752 u64 ten_fd : 1; 753 u64 ten_hd : 1; 754 u64 hun_t2fd : 1; 755 u64 hun_t2hd : 1; 756 u64 ext_st : 1; 757 u64 reserved_7_7 : 1; 758 u64 prb_sup : 1; 759 u64 an_cpt : 1; 760 u64 rm_flt : 1; 761 u64 an_abil : 1; 762 u64 lnk_st : 1; 763 u64 reserved_1_1 : 1; 764 u64 extnd : 1; 765 } s; 766 struct cvmx_pcsx_mrx_status_reg_s cn52xx; 767 struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; 768 struct cvmx_pcsx_mrx_status_reg_s cn56xx; 769 struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; 770 struct cvmx_pcsx_mrx_status_reg_s cn61xx; 771 struct cvmx_pcsx_mrx_status_reg_s cn63xx; 772 struct cvmx_pcsx_mrx_status_reg_s cn63xxp1; 773 struct cvmx_pcsx_mrx_status_reg_s cn66xx; 774 struct cvmx_pcsx_mrx_status_reg_s cn68xx; 775 struct cvmx_pcsx_mrx_status_reg_s cn68xxp1; 776 struct cvmx_pcsx_mrx_status_reg_s cn70xx; 777 struct cvmx_pcsx_mrx_status_reg_s cn70xxp1; 778 struct cvmx_pcsx_mrx_status_reg_s cnf71xx; 779}; 780 781typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t; 782 783/** 784 * cvmx_pcs#_rx#_states_reg 785 * 786 * PCS_RX_STATES_REG = RX State Machines states register 787 * 788 */ 789union cvmx_pcsx_rxx_states_reg { 790 u64 u64; 791 struct cvmx_pcsx_rxx_states_reg_s { 792 u64 reserved_16_63 : 48; 793 u64 rx_bad : 1; 794 u64 rx_st : 5; 795 u64 sync_bad : 1; 796 u64 sync : 4; 797 u64 an_bad : 1; 798 u64 an_st : 4; 799 } s; 800 struct cvmx_pcsx_rxx_states_reg_s cn52xx; 801 struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; 802 struct cvmx_pcsx_rxx_states_reg_s cn56xx; 803 struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; 804 struct cvmx_pcsx_rxx_states_reg_s cn61xx; 805 struct cvmx_pcsx_rxx_states_reg_s cn63xx; 806 struct cvmx_pcsx_rxx_states_reg_s cn63xxp1; 807 struct cvmx_pcsx_rxx_states_reg_s cn66xx; 808 struct cvmx_pcsx_rxx_states_reg_s cn68xx; 809 struct cvmx_pcsx_rxx_states_reg_s cn68xxp1; 810 struct cvmx_pcsx_rxx_states_reg_s cn70xx; 811 struct cvmx_pcsx_rxx_states_reg_s cn70xxp1; 812 struct cvmx_pcsx_rxx_states_reg_s cnf71xx; 813}; 814 815typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t; 816 817/** 818 * cvmx_pcs#_rx#_sync_reg 819 * 820 * Note: 821 * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved. 822 * 823 * 824 * PCS_RX_SYNC_REG = Code Group synchronization reg 825 */ 826union cvmx_pcsx_rxx_sync_reg { 827 u64 u64; 828 struct cvmx_pcsx_rxx_sync_reg_s { 829 u64 reserved_2_63 : 62; 830 u64 sync : 1; 831 u64 bit_lock : 1; 832 } s; 833 struct cvmx_pcsx_rxx_sync_reg_s cn52xx; 834 struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; 835 struct cvmx_pcsx_rxx_sync_reg_s cn56xx; 836 struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; 837 struct cvmx_pcsx_rxx_sync_reg_s cn61xx; 838 struct cvmx_pcsx_rxx_sync_reg_s cn63xx; 839 struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1; 840 struct cvmx_pcsx_rxx_sync_reg_s cn66xx; 841 struct cvmx_pcsx_rxx_sync_reg_s cn68xx; 842 struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1; 843 struct cvmx_pcsx_rxx_sync_reg_s cn70xx; 844 struct cvmx_pcsx_rxx_sync_reg_s cn70xxp1; 845 struct cvmx_pcsx_rxx_sync_reg_s cnf71xx; 846}; 847 848typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t; 849 850/** 851 * cvmx_pcs#_serdes_crdt_cnt#_reg 852 * 853 * PCS SERDES Credit Count 854 * 855 */ 856union cvmx_pcsx_serdes_crdt_cntx_reg { 857 u64 u64; 858 struct cvmx_pcsx_serdes_crdt_cntx_reg_s { 859 u64 reserved_5_63 : 59; 860 u64 cnt : 5; 861 } s; 862 struct cvmx_pcsx_serdes_crdt_cntx_reg_s cn70xx; 863 struct cvmx_pcsx_serdes_crdt_cntx_reg_s cn70xxp1; 864}; 865 866typedef union cvmx_pcsx_serdes_crdt_cntx_reg cvmx_pcsx_serdes_crdt_cntx_reg_t; 867 868/** 869 * cvmx_pcs#_sgm#_an_adv_reg 870 * 871 * SGMII AN Advertisement Register (sent out as tx_config_reg) 872 * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the 873 * MAC_PHY mode bit in misc_ctl_reg 874 * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit 875 * and [0] is always 1. 876 * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results. 877 */ 878union cvmx_pcsx_sgmx_an_adv_reg { 879 u64 u64; 880 struct cvmx_pcsx_sgmx_an_adv_reg_s { 881 u64 reserved_16_63 : 48; 882 u64 link : 1; 883 u64 ack : 1; 884 u64 reserved_13_13 : 1; 885 u64 dup : 1; 886 u64 speed : 2; 887 u64 reserved_1_9 : 9; 888 u64 one : 1; 889 } s; 890 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; 891 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; 892 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; 893 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; 894 struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx; 895 struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx; 896 struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1; 897 struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx; 898 struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx; 899 struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1; 900 struct cvmx_pcsx_sgmx_an_adv_reg_s cn70xx; 901 struct cvmx_pcsx_sgmx_an_adv_reg_s cn70xxp1; 902 struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx; 903}; 904 905typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t; 906 907/** 908 * cvmx_pcs#_sgm#_lp_adv_reg 909 * 910 * SGMII LP Advertisement Register (received as rx_config_reg) 911 * 912 */ 913union cvmx_pcsx_sgmx_lp_adv_reg { 914 u64 u64; 915 struct cvmx_pcsx_sgmx_lp_adv_reg_s { 916 u64 reserved_16_63 : 48; 917 u64 link : 1; 918 u64 reserved_13_14 : 2; 919 u64 dup : 1; 920 u64 speed : 2; 921 u64 reserved_1_9 : 9; 922 u64 one : 1; 923 } s; 924 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; 925 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; 926 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; 927 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; 928 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx; 929 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx; 930 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1; 931 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx; 932 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx; 933 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1; 934 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn70xx; 935 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn70xxp1; 936 struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx; 937}; 938 939typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t; 940 941/** 942 * cvmx_pcs#_tx#_states_reg 943 * 944 * PCS_TX_STATES_REG = TX State Machines states register 945 * 946 */ 947union cvmx_pcsx_txx_states_reg { 948 u64 u64; 949 struct cvmx_pcsx_txx_states_reg_s { 950 u64 reserved_7_63 : 57; 951 u64 xmit : 2; 952 u64 tx_bad : 1; 953 u64 ord_st : 4; 954 } s; 955 struct cvmx_pcsx_txx_states_reg_s cn52xx; 956 struct cvmx_pcsx_txx_states_reg_s cn52xxp1; 957 struct cvmx_pcsx_txx_states_reg_s cn56xx; 958 struct cvmx_pcsx_txx_states_reg_s cn56xxp1; 959 struct cvmx_pcsx_txx_states_reg_s cn61xx; 960 struct cvmx_pcsx_txx_states_reg_s cn63xx; 961 struct cvmx_pcsx_txx_states_reg_s cn63xxp1; 962 struct cvmx_pcsx_txx_states_reg_s cn66xx; 963 struct cvmx_pcsx_txx_states_reg_s cn68xx; 964 struct cvmx_pcsx_txx_states_reg_s cn68xxp1; 965 struct cvmx_pcsx_txx_states_reg_s cn70xx; 966 struct cvmx_pcsx_txx_states_reg_s cn70xxp1; 967 struct cvmx_pcsx_txx_states_reg_s cnf71xx; 968}; 969 970typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t; 971 972/** 973 * cvmx_pcs#_tx_rx#_polarity_reg 974 * 975 * Note: 976 * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after 977 * code grp synchronization is achieved. 978 */ 979union cvmx_pcsx_tx_rxx_polarity_reg { 980 u64 u64; 981 struct cvmx_pcsx_tx_rxx_polarity_reg_s { 982 u64 reserved_4_63 : 60; 983 u64 rxovrd : 1; 984 u64 autorxpl : 1; 985 u64 rxplrt : 1; 986 u64 txplrt : 1; 987 } s; 988 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; 989 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; 990 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; 991 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; 992 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx; 993 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx; 994 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1; 995 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx; 996 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx; 997 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1; 998 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn70xx; 999 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn70xxp1; 1000 struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx; 1001}; 1002 1003typedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t; 1004 1005#endif 1006