1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 */
5
6#ifndef __CVMX_MIO_EMM_DEFS_H__
7#define __CVMX_MIO_EMM_DEFS_H__
8
9static inline u64 MIO_EMM_DMA_FIFO_CFG(void)
10{
11	return 0x160;
12}
13
14static inline u64 MIO_EMM_DMA_FIFO_ADR(void)
15{
16	return 0x170;
17}
18
19static inline u64 MIO_EMM_DMA_FIFO_CMD(void)
20{
21	return 0x178;
22}
23
24static inline u64 MIO_EMM_DMA_CFG(void)
25{
26	return 0x180;
27}
28
29static inline u64 MIO_EMM_DMA_ADR(void)
30{
31	return 0x188;
32}
33
34static inline u64 MIO_EMM_DMA_INT(void)
35{
36	return 0x190;
37}
38
39static inline u64 MIO_EMM_CFG(void)
40{
41	return 0x2000;
42}
43
44static inline u64 MIO_EMM_MODEX(u64 a)
45{
46	return 0x2008 + 8 * a;
47}
48
49static inline u64 MIO_EMM_SWITCH(void)
50{
51	return 0x2048;
52}
53
54static inline u64 MIO_EMM_DMA(void)
55{
56	return 0x2050;
57}
58
59static inline u64 MIO_EMM_CMD(void)
60{
61	return 0x2058;
62}
63
64static inline u64 MIO_EMM_RSP_STS(void)
65{
66	return 0x2060;
67}
68
69static inline u64 MIO_EMM_RSP_LO(void)
70{
71	return 0x2068;
72}
73
74static inline u64 MIO_EMM_RSP_HI(void)
75{
76	return 0x2070;
77}
78
79static inline u64 MIO_EMM_INT(void)
80{
81	return 0x2078;
82}
83
84static inline u64 MIO_EMM_WDOG(void)
85{
86	return 0x2088;
87}
88
89static inline u64 MIO_EMM_SAMPLE(void)
90{
91	return 0x2090;
92}
93
94static inline u64 MIO_EMM_STS_MASK(void)
95{
96	return 0x2098;
97}
98
99static inline u64 MIO_EMM_RCA(void)
100{
101	return 0x20a0;
102}
103
104static inline u64 MIO_EMM_BUF_IDX(void)
105{
106	return 0x20e0;
107}
108
109static inline u64 MIO_EMM_BUF_DAT(void)
110{
111	return 0x20e8;
112}
113
114/* Dummy implementation, not documented on MIPS Octeon */
115static inline u64 MIO_EMM_DEBUG(void)
116{
117	return 0x20f8;
118}
119
120/**
121 * mio_emm_access_wdog
122 */
123union mio_emm_access_wdog {
124	u64 u;
125	struct mio_emm_access_wdog_s {
126		uint64_t reserved_32_63 : 32;
127		uint64_t clk_cnt : 32;
128	} s;
129};
130
131/**
132 * mio_emm_buf_dat
133 *
134 * MIO_EMM_BUF_DAT = MIO EMMC Data buffer access Register
135 *
136 */
137union mio_emm_buf_dat {
138	u64 u;
139	struct mio_emm_buf_dat_s {
140		uint64_t dat : 64;
141	} s;
142};
143
144/**
145 * mio_emm_buf_idx
146 *
147 * MIO_EMM_BUF_IDX = MIO EMMC Data buffer address Register
148 *
149 */
150union mio_emm_buf_idx {
151	u64 u;
152	struct mio_emm_buf_idx_s {
153		uint64_t reserved_17_63 : 47;
154		uint64_t inc : 1;
155		uint64_t reserved_7_15 : 9;
156		uint64_t buf_num : 1;
157		uint64_t offset : 6;
158	} s;
159};
160
161/**
162 * mio_emm_cfg
163 *
164 * MIO_EMM_CFG = MIO EMMC Configuration Register
165 *
166 */
167union mio_emm_cfg {
168	u64 u;
169	struct mio_emm_cfg_s {
170		uint64_t reserved_17_63 : 47;
171		uint64_t boot_fail : 1;
172		uint64_t reserved_4_15 : 12;
173		uint64_t bus_ena : 4;
174	} s;
175};
176
177/**
178 * mio_emm_cmd
179 *
180 * MIO_EMM_CMD = MIO EMMC Command Register
181 *
182 */
183union mio_emm_cmd {
184	u64 u;
185	struct mio_emm_cmd_s {
186		uint64_t reserved_63_63 : 1;
187		uint64_t skip_busy : 1;
188		uint64_t bus_id : 2;
189		uint64_t cmd_val : 1;
190		uint64_t reserved_56_58 : 3;
191		uint64_t dbuf : 1;
192		uint64_t offset : 6;
193		uint64_t reserved_43_48 : 6;
194		uint64_t ctype_xor : 2;
195		uint64_t rtype_xor : 3;
196		uint64_t cmd_idx : 6;
197		uint64_t arg : 32;
198	} s;
199};
200
201/**
202 * mio_emm_dma
203 *
204 * MIO_EMM_DMA = MIO EMMC DMA config Register
205 *
206 */
207union mio_emm_dma {
208	u64 u;
209	struct mio_emm_dma_s {
210		uint64_t reserved_63_63 : 1;
211		uint64_t skip_busy : 1;
212		uint64_t bus_id : 2;
213		uint64_t dma_val : 1;
214		uint64_t sector : 1;
215		uint64_t dat_null : 1;
216		uint64_t thres : 6;
217		uint64_t rel_wr : 1;
218		uint64_t rw : 1;
219		uint64_t multi : 1;
220		uint64_t block_cnt : 16;
221		uint64_t card_addr : 32;
222	} s;
223};
224
225/**
226 * mio_emm_dma_adr
227 *
228 * This register sets the address for eMMC/SD flash transfers to/from memory. Sixty-four-bit
229 * operations must be used to access this register. This register is updated by the DMA
230 * hardware and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR.
231 */
232union mio_emm_dma_adr {
233	u64 u;
234	struct mio_emm_dma_adr_s {
235		uint64_t reserved_42_63 : 22;
236		uint64_t adr : 42;
237	} s;
238};
239
240/**
241 * mio_emm_dma_cfg
242 *
243 * This register controls the internal DMA engine used with the eMMC/SD flash controller. Sixty-
244 * four-bit operations must be used to access this register. This register is updated by the
245 * hardware DMA engine and can also be reloaded by writes to the MIO_EMM_DMA_FIFO_CMD register.
246 */
247union mio_emm_dma_cfg {
248	u64 u;
249	struct mio_emm_dma_cfg_s {
250		uint64_t en : 1;
251		uint64_t rw : 1;
252		uint64_t clr : 1;
253		uint64_t reserved_60_60 : 1;
254		uint64_t swap32 : 1;
255		uint64_t swap16 : 1;
256		uint64_t swap8 : 1;
257		uint64_t endian : 1;
258		uint64_t size : 20;
259		uint64_t reserved_0_35 : 36;
260	} s;
261};
262
263/**
264 * mio_emm_dma_fifo_adr
265 *
266 * This register specifies the internal address that is loaded into the eMMC internal DMA FIFO.
267 * The FIFO is used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA
268 * completes successfully.
269 */
270union mio_emm_dma_fifo_adr {
271	u64 u;
272	struct mio_emm_dma_fifo_adr_s {
273		uint64_t reserved_42_63 : 22;
274		uint64_t adr : 39;
275		uint64_t reserved_0_2 : 3;
276	} s;
277};
278
279/**
280 * mio_emm_dma_fifo_cfg
281 *
282 * This register controls DMA FIFO operations.
283 *
284 */
285union mio_emm_dma_fifo_cfg {
286	u64 u;
287	struct mio_emm_dma_fifo_cfg_s {
288		uint64_t reserved_17_63 : 47;
289		uint64_t clr : 1;
290		uint64_t reserved_13_15 : 3;
291		uint64_t int_lvl : 5;
292		uint64_t reserved_5_7 : 3;
293		uint64_t count : 5;
294	} s;
295};
296
297/**
298 * mio_emm_dma_fifo_cmd
299 *
300 * This register specifies a command that is loaded into the eMMC internal DMA FIFO.  The FIFO is
301 * used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes
302 * successfully. Writes to this register store both the MIO_EMM_DMA_FIFO_CMD and the
303 * MIO_EMM_DMA_FIFO_ADR contents into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT]
304 * field.
305 *
306 * Note: This register has a similar format to MIO_EMM_DMA_CFG with the exception
307 * that the EN and CLR fields are absent. These are supported in MIO_EMM_DMA_FIFO_CFG.
308 */
309union mio_emm_dma_fifo_cmd {
310	u64 u;
311	struct mio_emm_dma_fifo_cmd_s {
312		uint64_t reserved_63_63 : 1;
313		uint64_t rw : 1;
314		uint64_t reserved_61_61 : 1;
315		uint64_t intdis : 1;
316		uint64_t swap32 : 1;
317		uint64_t swap16 : 1;
318		uint64_t swap8 : 1;
319		uint64_t endian : 1;
320		uint64_t size : 20;
321		uint64_t reserved_0_35 : 36;
322	} s;
323};
324
325/**
326 * mio_emm_dma_int
327 *
328 * Sixty-four-bit operations must be used to access this register.
329 *
330 */
331union mio_emm_dma_int {
332	u64 u;
333	struct mio_emm_dma_int_s {
334		uint64_t reserved_2_63 : 62;
335		uint64_t fifo : 1;
336		uint64_t done : 1;
337	} s;
338};
339
340/**
341 * mio_emm_dma_int_w1s
342 */
343union mio_emm_dma_int_w1s {
344	u64 u;
345	struct mio_emm_dma_int_w1s_s {
346		uint64_t reserved_2_63 : 62;
347		uint64_t fifo : 1;
348		uint64_t done : 1;
349	} s;
350};
351
352/**
353 * mio_emm_int
354 *
355 * MIO_EMM_INT = MIO EMMC Interrupt Register
356 *
357 */
358union mio_emm_int {
359	u64 u;
360	struct mio_emm_int_s {
361		uint64_t reserved_7_63 : 57;
362		uint64_t switch_err : 1;
363		uint64_t switch_done : 1;
364		uint64_t dma_err : 1;
365		uint64_t cmd_err : 1;
366		uint64_t dma_done : 1;
367		uint64_t cmd_done : 1;
368		uint64_t buf_done : 1;
369	} s;
370};
371
372/**
373 * mio_emm_int_en
374 *
375 * MIO_EMM_INT_EN = MIO EMMC Interrupt enable Register
376 *
377 */
378union mio_emm_int_en {
379	u64 u;
380	struct mio_emm_int_en_s {
381		uint64_t reserved_7_63 : 57;
382		uint64_t switch_err : 1;
383		uint64_t switch_done : 1;
384		uint64_t dma_err : 1;
385		uint64_t cmd_err : 1;
386		uint64_t dma_done : 1;
387		uint64_t cmd_done : 1;
388		uint64_t buf_done : 1;
389	} s;
390};
391
392/**
393 * mio_emm_int_w1s
394 */
395union mio_emm_int_w1s {
396	u64 u;
397	struct mio_emm_int_w1s_s {
398		uint64_t reserved_7_63 : 57;
399		uint64_t switch_err : 1;
400		uint64_t switch_done : 1;
401		uint64_t dma_err : 1;
402		uint64_t cmd_err : 1;
403		uint64_t dma_done : 1;
404		uint64_t cmd_done : 1;
405		uint64_t buf_done : 1;
406	} s;
407};
408
409/**
410 * mio_emm_mode#
411 *
412 * MIO_EMM_MODE = MIO EMMC Operating mode Register
413 *
414 */
415union mio_emm_modex {
416	u64 u;
417	struct mio_emm_modex_s {
418		uint64_t reserved_49_63 : 15;
419		uint64_t hs_timing : 1;
420		uint64_t reserved_43_47 : 5;
421		uint64_t bus_width : 3;
422		uint64_t reserved_36_39 : 4;
423		uint64_t power_class : 4;
424		uint64_t clk_hi : 16;
425		uint64_t clk_lo : 16;
426	} s;
427};
428
429/**
430 * mio_emm_rca
431 */
432union mio_emm_rca {
433	u64 u;
434	struct mio_emm_rca_s {
435		uint64_t reserved_16_63 : 48;
436		uint64_t card_rca : 16;
437	} s;
438};
439
440/**
441 * mio_emm_rsp_hi
442 *
443 * MIO_EMM_RSP_HI = MIO EMMC Response data high Register
444 *
445 */
446union mio_emm_rsp_hi {
447	u64 u;
448	struct mio_emm_rsp_hi_s {
449		uint64_t dat : 64;
450	} s;
451};
452
453/**
454 * mio_emm_rsp_lo
455 *
456 * MIO_EMM_RSP_LO = MIO EMMC Response data low Register
457 *
458 */
459union mio_emm_rsp_lo {
460	u64 u;
461	struct mio_emm_rsp_lo_s {
462		uint64_t dat : 64;
463	} s;
464};
465
466/**
467 * mio_emm_rsp_sts
468 *
469 * MIO_EMM_RSP_STS = MIO EMMC Response status Register
470 *
471 */
472union mio_emm_rsp_sts {
473	u64 u;
474	struct mio_emm_rsp_sts_s {
475		uint64_t reserved_62_63 : 2;
476		uint64_t bus_id : 2;
477		uint64_t cmd_val : 1;
478		uint64_t switch_val : 1;
479		uint64_t dma_val : 1;
480		uint64_t dma_pend : 1;
481		uint64_t acc_timeout : 1;
482		uint64_t reserved_29_54 : 26;
483		uint64_t dbuf_err : 1;
484		uint64_t reserved_24_27 : 4;
485		uint64_t dbuf : 1;
486		uint64_t blk_timeout : 1;
487		uint64_t blk_crc_err : 1;
488		uint64_t rsp_busybit : 1;
489		uint64_t stp_timeout : 1;
490		uint64_t stp_crc_err : 1;
491		uint64_t stp_bad_sts : 1;
492		uint64_t stp_val : 1;
493		uint64_t rsp_timeout : 1;
494		uint64_t rsp_crc_err : 1;
495		uint64_t rsp_bad_sts : 1;
496		uint64_t rsp_val : 1;
497		uint64_t rsp_type : 3;
498		uint64_t cmd_type : 2;
499		uint64_t cmd_idx : 6;
500		uint64_t cmd_done : 1;
501	} s;
502};
503
504/**
505 * mio_emm_sample
506 */
507union mio_emm_sample {
508	u64 u;
509	struct mio_emm_sample_s {
510		uint64_t reserved_26_63 : 38;
511		uint64_t cmd_cnt : 10;
512		uint64_t reserved_10_15 : 6;
513		uint64_t dat_cnt : 10;
514	} s;
515};
516
517/**
518 * mio_emm_sts_mask
519 */
520union mio_emm_sts_mask {
521	u64 u;
522	struct mio_emm_sts_mask_s {
523		uint64_t reserved_32_63 : 32;
524		uint64_t sts_msk : 32;
525	} s;
526};
527
528/**
529 * mio_emm_switch
530 *
531 * MIO_EMM_SWITCH = MIO EMMC Operating mode switch Register
532 *
533 */
534union mio_emm_switch {
535	u64 u;
536	struct mio_emm_switch_s {
537		uint64_t reserved_62_63 : 2;
538		uint64_t bus_id : 2;
539		uint64_t switch_exe : 1;
540		uint64_t switch_err0 : 1;
541		uint64_t switch_err1 : 1;
542		uint64_t switch_err2 : 1;
543		uint64_t reserved_49_55 : 7;
544		uint64_t hs_timing : 1;
545		uint64_t reserved_43_47 : 5;
546		uint64_t bus_width : 3;
547		uint64_t reserved_36_39 : 4;
548		uint64_t power_class : 4;
549		uint64_t clk_hi : 16;
550		uint64_t clk_lo : 16;
551	} s;
552};
553
554/**
555 * mio_emm_wdog
556 *
557 * MIO_EMM_WDOG = MIO EMMC Watchdog Register
558 *
559 */
560union mio_emm_wdog {
561	u64 u;
562	struct mio_emm_wdog_s {
563		uint64_t reserved_26_63 : 38;
564		uint64_t clk_cnt : 26;
565	} s;
566};
567
568/*
569 * The following structs are only available to enable compilation of the common
570 * MMC driver. These registers do not exist on MIPS Octeon.
571 */
572
573/**
574 * Register (RSL) mio_emm_timing
575 *
576 * eMMC Timing Register This register determines the number of tap delays
577 * the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in
578 * relation to EMM_CLK. These values should only be changed when the eMMC
579 * bus is idle.
580 */
581union mio_emm_timing {
582	u64 u;
583	struct mio_emm_timing_s {
584		u64 data_out_tap                     : 6;
585		u64 reserved_6_15                    : 10;
586		u64 data_in_tap                      : 6;
587		u64 reserved_22_31                   : 10;
588		u64 cmd_out_tap                      : 6;
589		u64 reserved_38_47                   : 10;
590		u64 cmd_in_tap                       : 6;
591		u64 reserved_54_63                   : 10;
592	} s;
593};
594
595/**
596 * Register (RSL) mio_emm_debug
597 *
598 * eMMC Debug Register
599 */
600union mio_emm_debug {
601	u64 u;
602	struct mio_emm_debug_s {
603		u64 clk_on                           : 1;
604		u64 reserved_1_7                     : 7;
605		u64 cmd_sm                           : 4;
606		u64 data_sm                          : 4;
607		u64 dma_sm                           : 4;
608		u64 emmc_clk_disable                 : 1;
609		u64 rdsync_rst                       : 1;
610		u64 reserved_22_63                   : 42;
611	} s;
612};
613
614#endif
615