1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2018-2022 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon lbk. 7 */ 8 9#ifndef __CVMX_LBK_DEFS_H__ 10#define __CVMX_LBK_DEFS_H__ 11 12#define CVMX_LBK_BIST_RESULT (0x0001180012000020ull) 13#define CVMX_LBK_CHX_PKIND(offset) (0x0001180012000200ull + ((offset) & 63) * 8) 14#define CVMX_LBK_CLK_GATE_CTL (0x0001180012000008ull) 15#define CVMX_LBK_DAT_ERR_INFO (0x0001180012000050ull) 16#define CVMX_LBK_ECC_CFG (0x0001180012000060ull) 17#define CVMX_LBK_INT (0x0001180012000040ull) 18#define CVMX_LBK_SFT_RST (0x0001180012000000ull) 19 20/** 21 * cvmx_lbk_bist_result 22 * 23 * This register provides access to the internal BIST results. Each bit is the 24 * BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 25 */ 26union cvmx_lbk_bist_result { 27 u64 u64; 28 struct cvmx_lbk_bist_result_s { 29 u64 reserved_1_63 : 63; 30 u64 dat : 1; 31 } s; 32 struct cvmx_lbk_bist_result_s cn73xx; 33 struct cvmx_lbk_bist_result_s cn78xx; 34 struct cvmx_lbk_bist_result_s cn78xxp1; 35 struct cvmx_lbk_bist_result_s cnf75xx; 36}; 37 38typedef union cvmx_lbk_bist_result cvmx_lbk_bist_result_t; 39 40/** 41 * cvmx_lbk_ch#_pkind 42 */ 43union cvmx_lbk_chx_pkind { 44 u64 u64; 45 struct cvmx_lbk_chx_pkind_s { 46 u64 reserved_6_63 : 58; 47 u64 pkind : 6; 48 } s; 49 struct cvmx_lbk_chx_pkind_s cn73xx; 50 struct cvmx_lbk_chx_pkind_s cn78xx; 51 struct cvmx_lbk_chx_pkind_s cn78xxp1; 52 struct cvmx_lbk_chx_pkind_s cnf75xx; 53}; 54 55typedef union cvmx_lbk_chx_pkind cvmx_lbk_chx_pkind_t; 56 57/** 58 * cvmx_lbk_clk_gate_ctl 59 * 60 * This register is for diagnostic use only. 61 * 62 */ 63union cvmx_lbk_clk_gate_ctl { 64 u64 u64; 65 struct cvmx_lbk_clk_gate_ctl_s { 66 u64 reserved_1_63 : 63; 67 u64 dis : 1; 68 } s; 69 struct cvmx_lbk_clk_gate_ctl_s cn73xx; 70 struct cvmx_lbk_clk_gate_ctl_s cn78xx; 71 struct cvmx_lbk_clk_gate_ctl_s cn78xxp1; 72 struct cvmx_lbk_clk_gate_ctl_s cnf75xx; 73}; 74 75typedef union cvmx_lbk_clk_gate_ctl cvmx_lbk_clk_gate_ctl_t; 76 77/** 78 * cvmx_lbk_dat_err_info 79 */ 80union cvmx_lbk_dat_err_info { 81 u64 u64; 82 struct cvmx_lbk_dat_err_info_s { 83 u64 reserved_58_63 : 6; 84 u64 dbe_ecc_out : 9; 85 u64 dbe_synd : 9; 86 u64 dbe_addr : 8; 87 u64 reserved_26_31 : 6; 88 u64 sbe_ecc_out : 9; 89 u64 sbe_synd : 9; 90 u64 sbe_addr : 8; 91 } s; 92 struct cvmx_lbk_dat_err_info_s cn73xx; 93 struct cvmx_lbk_dat_err_info_s cn78xx; 94 struct cvmx_lbk_dat_err_info_s cn78xxp1; 95 struct cvmx_lbk_dat_err_info_s cnf75xx; 96}; 97 98typedef union cvmx_lbk_dat_err_info cvmx_lbk_dat_err_info_t; 99 100/** 101 * cvmx_lbk_ecc_cfg 102 */ 103union cvmx_lbk_ecc_cfg { 104 u64 u64; 105 struct cvmx_lbk_ecc_cfg_s { 106 u64 reserved_3_63 : 61; 107 u64 dat_flip : 2; 108 u64 dat_cdis : 1; 109 } s; 110 struct cvmx_lbk_ecc_cfg_s cn73xx; 111 struct cvmx_lbk_ecc_cfg_s cn78xx; 112 struct cvmx_lbk_ecc_cfg_s cn78xxp1; 113 struct cvmx_lbk_ecc_cfg_s cnf75xx; 114}; 115 116typedef union cvmx_lbk_ecc_cfg cvmx_lbk_ecc_cfg_t; 117 118/** 119 * cvmx_lbk_int 120 */ 121union cvmx_lbk_int { 122 u64 u64; 123 struct cvmx_lbk_int_s { 124 u64 reserved_6_63 : 58; 125 u64 chan_oflow : 1; 126 u64 chan_uflow : 1; 127 u64 dat_oflow : 1; 128 u64 dat_uflow : 1; 129 u64 dat_dbe : 1; 130 u64 dat_sbe : 1; 131 } s; 132 struct cvmx_lbk_int_s cn73xx; 133 struct cvmx_lbk_int_s cn78xx; 134 struct cvmx_lbk_int_s cn78xxp1; 135 struct cvmx_lbk_int_s cnf75xx; 136}; 137 138typedef union cvmx_lbk_int cvmx_lbk_int_t; 139 140/** 141 * cvmx_lbk_sft_rst 142 */ 143union cvmx_lbk_sft_rst { 144 u64 u64; 145 struct cvmx_lbk_sft_rst_s { 146 u64 reserved_1_63 : 63; 147 u64 reset : 1; 148 } s; 149 struct cvmx_lbk_sft_rst_s cn73xx; 150 struct cvmx_lbk_sft_rst_s cn78xx; 151 struct cvmx_lbk_sft_rst_s cn78xxp1; 152 struct cvmx_lbk_sft_rst_s cnf75xx; 153}; 154 155typedef union cvmx_lbk_sft_rst cvmx_lbk_sft_rst_t; 156 157#endif 158