1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com> 4 * 5 * Based on QSDK 6 */ 7 8#include <asm/global_data.h> 9#include <asm/io.h> 10#include <asm/addrspace.h> 11#include <asm/types.h> 12#include <linux/delay.h> 13#include <mach/ar71xx_regs.h> 14#include <mach/ath79.h> 15 16#define DDR_FSM_WAIT_CTRL_VAL 0xa12 17#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30 18#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000 19#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) \ 20 (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) 21#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20 22#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000 23#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) \ 24 (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) 25#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19 26#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000 27#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) \ 28 (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) 29#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18 30#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000 31#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) \ 32 (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) 33#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17 34#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000 35#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) \ 36 (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) 37#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16 38#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000 39#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) \ 40 (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) 41#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB 15 42#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK 0x00008000 43#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(x) \ 44 (((x) << DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK) 45#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB 14 46#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK 0x00004000 47#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(x) \ 48 (((x) << DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK) 49#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6 50#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040 51#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) \ 52 (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) 53#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2 54#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004 55#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) \ 56 (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) 57#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1 58#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002 59#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) \ 60 (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) 61#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31 62#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000 63#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) \ 64 (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) 65#define DDR_CONFIG_OPEN_PAGE_LSB 30 66#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000 67#define DDR_CONFIG_OPEN_PAGE_SET(x) \ 68 (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK) 69#define DDR_CONFIG_CAS_LATENCY_LSB 27 70#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000 71#define DDR_CONFIG_CAS_LATENCY_SET(x) \ 72 (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK) 73#define DDR_CONFIG_TMRD_LSB 23 74#define DDR_CONFIG_TMRD_MASK 0x07800000 75#define DDR_CONFIG_TMRD_SET(x) \ 76 (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK) 77#define DDR_CONFIG_TRFC_LSB 17 78#define DDR_CONFIG_TRFC_MASK 0x007e0000 79#define DDR_CONFIG_TRFC_SET(x) \ 80 (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK) 81#define DDR_CONFIG_TRRD_LSB 13 82#define DDR_CONFIG_TRRD_MASK 0x0001e000 83#define DDR_CONFIG_TRRD_SET(x) \ 84 (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK) 85#define DDR_CONFIG_TRP_LSB 9 86#define DDR_CONFIG_TRP_MASK 0x00001e00 87#define DDR_CONFIG_TRP_SET(x) \ 88 (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK) 89#define DDR_CONFIG_TRCD_LSB 5 90#define DDR_CONFIG_TRCD_MASK 0x000001e0 91#define DDR_CONFIG_TRCD_SET(x) \ 92 (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK) 93#define DDR_CONFIG_TRAS_LSB 0 94#define DDR_CONFIG_TRAS_MASK 0x0000001f 95#define DDR_CONFIG_TRAS_SET(x) \ 96 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK) 97#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31 98#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000 99#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) \ 100 (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) 101#define DDR_CONFIG2_SWAP_A26_A27_LSB 30 102#define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000 103#define DDR_CONFIG2_SWAP_A26_A27_SET(x) \ 104 (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK) 105#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26 106#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000 107#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) \ 108 (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) 109#define DDR_CONFIG2_TWTR_LSB 21 110#define DDR_CONFIG2_TWTR_MASK 0x03e00000 111#define DDR_CONFIG2_TWTR_SET(x) \ 112 (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK) 113#define DDR_CONFIG2_TRTP_LSB 17 114#define DDR_CONFIG2_TRTP_MASK 0x001e0000 115#define DDR_CONFIG2_TRTP_SET(x) \ 116 (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK) 117#define DDR_CONFIG2_TRTW_LSB 12 118#define DDR_CONFIG2_TRTW_MASK 0x0001f000 119#define DDR_CONFIG2_TRTW_SET(x) \ 120 (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK) 121#define DDR_CONFIG2_TWR_LSB 8 122#define DDR_CONFIG2_TWR_MASK 0x00000f00 123#define DDR_CONFIG2_TWR_SET(x) \ 124 (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK) 125#define DDR_CONFIG2_CKE_LSB 7 126#define DDR_CONFIG2_CKE_MASK 0x00000080 127#define DDR_CONFIG2_CKE_SET(x) \ 128 (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK) 129#define DDR_CONFIG2_CNTL_OE_EN_LSB 5 130#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020 131#define DDR_CONFIG2_CNTL_OE_EN_SET(x) \ 132 (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK) 133#define DDR_CONFIG2_BURST_LENGTH_LSB 0 134#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f 135#define DDR_CONFIG2_BURST_LENGTH_SET(x) \ 136 (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK) 137#define RST_BOOTSTRAP_ADDRESS 0x180600b0 138#define PMU2_SWREGMSB_LSB 22 139#define PMU2_SWREGMSB_MASK 0xffc00000 140#define PMU2_SWREGMSB_SET(x) \ 141 (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK) 142#define PMU2_PGM_LSB 21 143#define PMU2_PGM_MASK 0x00200000 144#define PMU2_PGM_SET(x) \ 145 (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK) 146 147#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) 148 149/* 150* DDR2 DDR1 151* 0x40c3 25MHz 0x4186 25Mhz 152* 0x4138 40MHz 0x4270 40Mhz 153*/ 154#define CFG_DDR2_REFRESH_VAL 0x40c3 155#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \ 156 DDR_CONFIG_OPEN_PAGE_SET(0x1) | DDR_CONFIG_CAS_LATENCY_SET(0x4) | \ 157 DDR_CONFIG_TMRD_SET(0x6) | DDR_CONFIG_TRFC_SET(0x16) | \ 158 DDR_CONFIG_TRRD_SET(0x7) | DDR_CONFIG_TRP_SET(0xb) | \ 159 DDR_CONFIG_TRCD_SET(0xb) | DDR_CONFIG_TRAS_SET(0) 160#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \ 161 DDR_CONFIG2_SWAP_A26_A27_SET(0x0) | DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0xa) | \ 162 DDR_CONFIG2_TWTR_SET(0x16) | DDR_CONFIG2_TRTP_SET(0xa) | \ 163 DDR_CONFIG2_TRTW_SET(0xe) | DDR_CONFIG2_TWR_SET(0x2) | \ 164 DDR_CONFIG2_CKE_SET(0x1) | DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \ 165 DDR_CONFIG2_BURST_LENGTH_SET(0x8) 166 167#define CFG_DDR2_CONFIG3_VAL 0x0000000e 168#define CFG_DDR2_EXT_MODE_VAL1 0x782 169#define CFG_DDR2_EXT_MODE_VAL2 0x402 170#define CFG_DDR2_MODE_VAL_INIT 0xb53 171#define CFG_DDR2_MODE_VAL 0xa53 172#define CFG_DDR2_TAP_VAL 0x10 173#define CFG_DDR2_EN_TWL_VAL 0x00001e91 174#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff 175 176#define CFG_DDR_CTL_CONFIG DDR_CTL_CONFIG_SRAM_TSEL_SET(0x1) | \ 177 DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(0x1) | \ 178 DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(0x1) | \ 179 DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(0x1) | \ 180 DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(0x1) | \ 181 DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(0x1) | \ 182 DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \ 183 DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1) 184 185DECLARE_GLOBAL_DATA_PTR; 186 187void qca956x_ddr_init(void) 188{ 189 u32 ddr_config, ddr_config2, ddr_config3, mod_val, \ 190 mod_val_init, cycle_val, tap_val, ctl_config; 191 void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, 192 MAP_NOCACHE); 193 void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE, QCA956X_SRIF_SIZE, 194 MAP_NOCACHE); 195 196 ddr_config = CFG_DDR2_CONFIG_VAL; 197 ddr_config2 = CFG_DDR2_CONFIG2_VAL; 198 ddr_config3 = CFG_DDR2_CONFIG3_VAL; 199 mod_val_init = CFG_DDR2_MODE_VAL_INIT; 200 mod_val = CFG_DDR2_MODE_VAL; 201 tap_val = CFG_DDR2_TAP_VAL; 202 cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16; 203 ctl_config = CFG_DDR_CTL_CONFIG | DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) | 204 DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1) | CPU_DDR_SYNC_MODE; 205 206 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); 207 udelay(10); 208 209 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); 210 udelay(10); 211 212 writel(ctl_config, ddr_regs + QCA956X_DDR_REG_CTL_CONF); 213 udelay(10); 214 215 writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); 216 udelay(100); 217 218 writel(0x74444444, ddr_regs + QCA956X_DDR_REG_BURST); 219 udelay(100); 220 221 writel(0x44444444, ddr_regs + QCA956X_DDR_REG_BURST2); 222 udelay(100); 223 224 writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL); 225 udelay(100); 226 227 writel(0xfffff, ddr_regs + QCA956X_DDR_REG_TIMEOUT_MAX); 228 udelay(100); 229 230 writel(ddr_config, ddr_regs + AR71XX_DDR_REG_CONFIG); 231 udelay(100); 232 233 writel(ddr_config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); 234 udelay(100); 235 236 writel(ddr_config3, ddr_regs + QCA956X_DDR_REG_DDR3_CONFIG); 237 udelay(100); 238 239 writel(CFG_DDR2_EN_TWL_VAL, ddr_regs + QCA956X_DDR_REG_DDR2_CONFIG); 240 udelay(100); 241 242 writel(ddr_config2 | 0x80, ddr_regs + AR71XX_DDR_REG_CONFIG2); /* CKE Enable */ 243 udelay(100); 244 245 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */ 246 udelay(10); 247 248 writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR2); 249 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR2 */ 250 udelay(10); 251 252 writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR3); 253 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR3 */ 254 udelay(10); 255 256 /* EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled */ 257 writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR); 258 udelay(100); 259 260 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ 261 udelay(10); 262 263 writel(mod_val_init, ddr_regs + AR71XX_DDR_REG_MODE); 264 udelay(1000); 265 266 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR Write */ 267 udelay(10); 268 269 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */ 270 udelay(10); 271 272 writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */ 273 udelay(10); 274 275 writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */ 276 udelay(10); 277 278 /* Issue MRS to remove DLL out-of-reset */ 279 writel(mod_val, ddr_regs + AR71XX_DDR_REG_MODE); 280 udelay(100); 281 282 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR write */ 283 udelay(100); 284 285 writel(CFG_DDR2_EXT_MODE_VAL1, ddr_regs + AR71XX_DDR_REG_EMR); 286 udelay(100); 287 288 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ 289 udelay(100); 290 291 writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR); 292 udelay(100); 293 294 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ 295 udelay(100); 296 297 writel(CFG_DDR2_REFRESH_VAL, ddr_regs + AR71XX_DDR_REG_REFRESH); 298 udelay(100); 299 300 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); 301 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); 302 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL2); 303 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL3); 304 305 writel(0x633c8176, srif_regs + QCA956X_SRIF_PMU1_REG); 306 /* Set DDR2 Voltage to 1.8 volts */ 307 writel(PMU2_SWREGMSB_SET(0x40) | PMU2_PGM_SET(0x1), 308 srif_regs + QCA956X_SRIF_PMU2_REG); 309} 310