1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/gpio/gpio.h> 11#include "mt7620.dtsi" 12 13/ { 14 compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc"; 15 model = "MediaTek MT7620 RFB (WS2120)"; 16 17 aliases { 18 serial0 = &uartlite; 19 spi0 = &spi0; 20 }; 21 22 chosen { 23 stdout-path = &uartlite; 24 }; 25}; 26 27&uartlite { 28 status = "okay"; 29}; 30 31&pinctrl { 32 state_default: pin_state { 33 pleds { 34 groups = "ephy led", "wled"; 35 function = "led"; 36 }; 37 38 gpios { 39 groups = "uartf"; 40 function = "gpio"; 41 }; 42 }; 43 44 gsw_pins: gsw_pins { 45 mdio { 46 groups = "mdio"; 47 function = "mdio"; 48 }; 49 50 rgmii1 { 51 groups = "rgmii1"; 52 function = "rgmii1"; 53 }; 54 55 rgmii2 { 56 groups = "rgmii2"; 57 function = "rgmii2"; 58 }; 59 }; 60}; 61 62&spi0 { 63 status = "okay"; 64 num-cs = <2>; 65 66 spi-flash@0 { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 compatible = "jedec,spi-nor"; 70 spi-max-frequency = <25000000>; 71 reg = <0>; 72 }; 73}; 74 75ð { 76 status = "okay"; 77 78 pinctrl-names = "default"; 79 pinctrl-0 = <&gsw_pins>; 80 81 port4 { 82 phy-mode = "rgmii"; 83 phy-addr = <4>; 84 }; 85 86 port5 { 87 phy-mode = "rgmii"; 88 phy-addr = <5>; 89 }; 90}; 91 92&mmc { 93 bus-width = <4>; 94 cap-sd-highspeed; 95 96 status = "okay"; 97}; 98