1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> 4 * 5 */ 6 7#ifndef mcf5307_h 8#define mcf5307_h 9 10/* 11 * Size of internal RAM (RAMBAR) 12 */ 13#define INT_RAM_SIZE 4096 14 15/* Bit definitions and macros for SYPCR */ 16#define SYPCR_SWTAVAL 0x02 17#define SYPCR_SWTA 0x04 18#define SYPCR_SWT(x) ((x&0x3)<<3) 19#define SYPCR_SWP 0x20 20#define SYPCR_SWRI 0x40 21#define SYPCR_SWE 0x80 22 23/* Bit definitions and macros for CSMR */ 24#define CSMR_V 0x01 25#define CSMR_UD 0x02 26#define CSMR_UC 0x04 27#define CSMR_SD 0x08 28#define CSMR_SC 0x10 29#define CSMR_CI 0x20 30#define CSMR_AM 0x40 31#define CSMR_WP 0x100 32 33/* Bit definitions and macros for DACR (SDRAM) */ 34#define DACR_PM_CONTINUOUS 0x04 35#define DACR_IP_PRECHG_ALL 0x08 36#define DACR_PORT_SZ_32 0 37#define DACR_PORT_SZ_8 (1<<4) 38#define DACR_PORT_SZ_16 (2<<4) 39#define DACR_IMRS_INIT_CMD (1<<6) 40#define DACR_CMD_PIN(x) ((x&7)<<8) 41#define DACR_CASL(x) ((x&3)<<12) 42#define DACR_RE (1<<15) 43 44/* Bit definitions and macros for CSCR */ 45#define CSCR_BSTW 0x08 46#define CSCR_BSTR 0x10 47#define CSCR_BEM 0x20 48#define CSCR_PS(x) ((x&0x3)<<6) 49#define CSCR_AA 0x100 50#define CSCR_WS ((x&0xf)<<10) 51 52/* Bit definitions for the ICR family of registers */ 53#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ 54#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ 55#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ 56#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ 57#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ 58#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ 59#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ 60#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ 61#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ 62 63#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ 64#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ 65#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ 66#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ 67 68#endif /* mcf5307_h */ 69