1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * MCF5227x Internal Memory Map
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 */
8
9#ifndef __DSPI_H__
10#define __DSPI_H__
11
12/* DMA Serial Peripheral Interface (DSPI) */
13typedef struct dspi {
14	u32 mcr;	/* 0x00 */
15	u32 resv0;	/* 0x04 */
16	u32 tcr;	/* 0x08 */
17	u32 ctar[8];	/* 0x0C - 0x28 */
18	u32 sr;		/* 0x2C */
19	u32 irsr;	/* 0x30 */
20	u32 tfr;	/* 0x34 - PUSHR */
21	u16 resv1;	/* 0x38 */
22	u16 rfr;	/* 0x3A - POPR */
23	u32 tfdr[16];	/* 0x3C */
24	u32 rfdr[16];	/* 0x7C */
25} dspi_t;
26
27/* Module configuration */
28#define DSPI_MCR_MSTR			(0x80000000)
29#define DSPI_MCR_CSCK			(0x40000000)
30#define DSPI_MCR_DCONF(x)		(((x)&0x03)<<28)
31#define DSPI_MCR_FRZ			(0x08000000)
32#define DSPI_MCR_MTFE			(0x04000000)
33#define DSPI_MCR_PCSSE			(0x02000000)
34#define DSPI_MCR_ROOE			(0x01000000)
35#define DSPI_MCR_CSIS7			(0x00800000)
36#define DSPI_MCR_CSIS6			(0x00400000)
37#define DSPI_MCR_CSIS5			(0x00200000)
38#define DSPI_MCR_CSIS4			(0x00100000)
39#define DSPI_MCR_CSIS3			(0x00080000)
40#define DSPI_MCR_CSIS2			(0x00040000)
41#define DSPI_MCR_CSIS1			(0x00020000)
42#define DSPI_MCR_CSIS0			(0x00010000)
43#define DSPI_MCR_MDIS			(0x00004000)
44#define DSPI_MCR_DTXF			(0x00002000)
45#define DSPI_MCR_DRXF			(0x00001000)
46#define DSPI_MCR_CTXF			(0x00000800)
47#define DSPI_MCR_CRXF			(0x00000400)
48#define DSPI_MCR_SMPL_PT(x)		(((x)&0x03)<<8)
49#define DSPI_MCR_HALT			(0x00000001)
50
51/* Transfer count */
52#define DSPI_TCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
53
54/* Clock and transfer attributes */
55#define DSPI_CTAR_DBR			(0x80000000)
56#define DSPI_CTAR_TRSZ(x)		(((x)&0x0F)<<27)
57#define DSPI_CTAR_CPOL			(0x04000000)
58#define DSPI_CTAR_CPHA			(0x02000000)
59#define DSPI_CTAR_LSBFE			(0x01000000)
60#define DSPI_CTAR_PCSSCK(x)		(((x)&0x03)<<22)
61#define DSPI_CTAR_PCSSCK_7CLK		(0x00A00000)
62#define DSPI_CTAR_PCSSCK_5CLK		(0x00800000)
63#define DSPI_CTAR_PCSSCK_3CLK		(0x00400000)
64#define DSPI_CTAR_PCSSCK_1CLK		(0x00000000)
65#define DSPI_CTAR_PASC(x)		(((x)&0x03)<<20)
66#define DSPI_CTAR_PASC_7CLK		(0x00300000)
67#define DSPI_CTAR_PASC_5CLK		(0x00200000)
68#define DSPI_CTAR_PASC_3CLK		(0x00100000)
69#define DSPI_CTAR_PASC_1CLK		(0x00000000)
70#define DSPI_CTAR_PDT(x)		(((x)&0x03)<<18)
71#define DSPI_CTAR_PDT_7CLK		(0x000A0000)
72#define DSPI_CTAR_PDT_5CLK		(0x00080000)
73#define DSPI_CTAR_PDT_3CLK		(0x00040000)
74#define DSPI_CTAR_PDT_1CLK		(0x00000000)
75#define DSPI_CTAR_PBR(x)		(((x)&0x03)<<16)
76#define DSPI_CTAR_PBR_7CLK		(0x00030000)
77#define DSPI_CTAR_PBR_5CLK		(0x00020000)
78#define DSPI_CTAR_PBR_3CLK		(0x00010000)
79#define DSPI_CTAR_PBR_1CLK		(0x00000000)
80#define DSPI_CTAR_CSSCK(x)		(((x)&0x0F)<<12)
81#define DSPI_CTAR_ASC(x)		(((x)&0x0F)<<8)
82#define DSPI_CTAR_DT(x)			(((x)&0x0F)<<4)
83#define DSPI_CTAR_BR(x)			(((x)&0x0F))
84
85/* Status */
86#define DSPI_SR_TCF			(0x80000000)
87#define DSPI_SR_TXRXS			(0x40000000)
88#define DSPI_SR_EOQF			(0x10000000)
89#define DSPI_SR_TFUF			(0x08000000)
90#define DSPI_SR_TFFF			(0x02000000)
91#define DSPI_SR_RFOF			(0x00080000)
92#define DSPI_SR_RFDF			(0x00020000)
93#define DSPI_SR_TXCTR(x)		(((x)&0x0F)<<12)
94#define DSPI_SR_TXPTR(x)		(((x)&0x0F)<<8)
95#define DSPI_SR_RXCTR(x)		(((x)&0x0F)<<4)
96#define DSPI_SR_RXPTR(x)		(((x)&0x0F))
97
98/* DMA/interrupt request selct and enable */
99#define DSPI_IRSR_TCFE			(0x80000000)
100#define DSPI_IRSR_EOQFE			(0x10000000)
101#define DSPI_IRSR_TFUFE			(0x08000000)
102#define DSPI_IRSR_TFFFE			(0x02000000)
103#define DSPI_IRSR_TFFFS			(0x01000000)
104#define DSPI_IRSR_RFOFE			(0x00080000)
105#define DSPI_IRSR_RFDFE			(0x00020000)
106#define DSPI_IRSR_RFDFS			(0x00010000)
107
108/* Transfer control - 32-bit access */
109#define DSPI_TFR_CONT			(0x80000000)
110#define DSPI_TFR_CTAS(x)		(((x)&0x07)<<12)
111#define DSPI_TFR_EOQ			(0x08000000)
112#define DSPI_TFR_CTCNT			(0x04000000)
113#define DSPI_TFR_CS7			(0x00800000)
114#define DSPI_TFR_CS6			(0x00400000)
115#define DSPI_TFR_CS5			(0x00200000)
116#define DSPI_TFR_CS4			(0x00100000)
117#define DSPI_TFR_CS3			(0x00080000)
118#define DSPI_TFR_CS2			(0x00040000)
119#define DSPI_TFR_CS1			(0x00020000)
120#define DSPI_TFR_CS0			(0x00010000)
121
122/* Transfer Fifo */
123#define DSPI_TFR_TXDATA(x)		(((x)&0xFFFF))
124
125/* Bit definitions and macros for DRFR */
126#define DSPI_RFR_RXDATA(x)		(((x)&0xFFFF))
127
128/* Bit definitions and macros for DTFDR group */
129#define DSPI_TFDR_TXDATA(x)		(((x)&0x0000FFFF))
130#define DSPI_TFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
131
132/* Bit definitions and macros for DRFDR group */
133#define DSPI_RFDR_RXDATA(x)		(((x)&0x0000FFFF))
134
135/* Architecture-related operations */
136void dspi_chip_select(int cs);
137void dspi_chip_unselect(int cs);
138
139#endif				/* __DSPI_H__ */
140