1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2003 4 * Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * MCF5282 additionals 7 * (C) Copyright 2005 8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 9 * (c) Copyright 2010 10 * Arcturus Networks Inc. <www.arcturusnetworks.com> 11 * 12 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 13 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 14 * Hayden Fraser (Hayden.Fraser@freescale.com) 15 * 16 * MCF5275 additions 17 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 18 */ 19 20#include <config.h> 21#include <cpu_func.h> 22#include <init.h> 23#include <watchdog.h> 24#include <asm/immap.h> 25#include <asm/io.h> 26 27#if defined(CONFIG_CMD_NET) 28#include <net.h> 29#include <asm/fec.h> 30#endif 31 32#ifndef CONFIG_M5272 33/* Only 5272 Flexbus chipselect is different from the rest */ 34void init_fbcs(void) 35{ 36 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); 37 38#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ 39 && defined(CFG_SYS_CS0_CTRL)) 40 out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); 41 out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); 42 out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); 43#else 44#warning "Chip Select 0 are not initialized/used" 45#endif 46#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ 47 && defined(CFG_SYS_CS1_CTRL)) 48 out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); 49 out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); 50 out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); 51#endif 52#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ 53 && defined(CFG_SYS_CS2_CTRL)) 54 out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); 55 out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); 56 out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); 57#endif 58#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ 59 && defined(CFG_SYS_CS3_CTRL)) 60 out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); 61 out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); 62 out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); 63#endif 64#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 65 && defined(CONFIG_SYS_CS4_CTRL)) 66 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 67 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 68 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 69#endif 70#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 71 && defined(CONFIG_SYS_CS5_CTRL)) 72 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 73 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 74 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 75#endif 76#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ 77 && defined(CONFIG_SYS_CS6_CTRL)) 78 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); 79 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); 80 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); 81#endif 82#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ 83 && defined(CONFIG_SYS_CS7_CTRL)) 84 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); 85 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); 86 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); 87#endif 88} 89#endif 90 91#if defined(CONFIG_M5208) 92void cpu_init_f(void) 93{ 94 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 95 96#ifndef CONFIG_WATCHDOG 97 wdog_t *wdg = (wdog_t *) MMAP_WDOG; 98 99 /* Disable the watchdog if we aren't using it */ 100 out_be16(&wdg->cr, 0); 101#endif 102 103 out_be32(&scm1->mpr, 0x77777777); 104 out_be32(&scm1->pacra, 0); 105 out_be32(&scm1->pacrb, 0); 106 out_be32(&scm1->pacrc, 0); 107 out_be32(&scm1->pacrd, 0); 108 out_be32(&scm1->pacre, 0); 109 out_be32(&scm1->pacrf, 0); 110 111 /* FlexBus Chipselect */ 112 init_fbcs(); 113 114 icache_enable(); 115} 116 117/* initialize higher level parts of CPU like timers */ 118int cpu_init_r(void) 119{ 120 return (0); 121} 122 123void uart_port_conf(int port) 124{ 125 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 126 127 /* Setup Ports: */ 128 switch (port) { 129 case 0: 130 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); 131 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 132 break; 133 case 1: 134 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); 135 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); 136 break; 137 case 2: 138#ifdef CONFIG_SYS_UART2_PRI_GPIO 139 clrbits_8(&gpio->par_timer, 140 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK)); 141 setbits_8(&gpio->par_timer, 142 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); 143#endif 144#ifdef CONFIG_SYS_UART2_ALT1_GPIO 145 clrbits_8(&gpio->par_feci2c, 146 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK)); 147 setbits_8(&gpio->par_feci2c, 148 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); 149#endif 150#ifdef CONFIG_SYS_UART2_ALT1_GPIO 151 clrbits_8(&gpio->par_feci2c, 152 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK)); 153 setbits_8(&gpio->par_feci2c, 154 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); 155#endif 156 break; 157 } 158} 159 160#if defined(CONFIG_CMD_NET) 161int fecpin_setclear(fec_info_t *info, int setclear) 162{ 163 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 164 165 if (setclear) { 166 setbits_8(&gpio->par_fec, 167 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 168 setbits_8(&gpio->par_feci2c, 169 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO); 170 } else { 171 clrbits_8(&gpio->par_fec, 172 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK)); 173 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK); 174 } 175 return 0; 176} 177#endif /* CONFIG_CMD_NET */ 178#endif /* CONFIG_M5208 */ 179 180#if defined(CONFIG_M5253) 181/* 182 * Breath some life into the CPU... 183 * 184 * Set up the memory map, 185 * initialize a bunch of registers, 186 * initialize the UPM's 187 */ 188void cpu_init_f(void) 189{ 190 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ 191 mbar_writeByte(MCFSIM_SYPCR, 0x00); 192 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 193 mbar_writeByte(MCFSIM_SWSR, 0x00); 194 mbar_writeByte(MCFSIM_SWDICR, 0x00); 195 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 196 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 197 mbar_writeByte(MCFSIM_I2CICR, 0x00); 198 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 199 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 200 mbar_writeByte(MCFSIM_ICR6, 0x00); 201 mbar_writeByte(MCFSIM_ICR7, 0x00); 202 mbar_writeByte(MCFSIM_ICR8, 0x00); 203 mbar_writeByte(MCFSIM_ICR9, 0x00); 204 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 205 206 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 207 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 208 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 209 210 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ 211 212 /* FlexBus Chipselect */ 213 init_fbcs(); 214 215#ifdef CONFIG_SYS_I2C_FSL 216 CFG_SYS_I2C_PINMUX_REG = 217 CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR; 218 CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; 219#ifdef CONFIG_SYS_I2C2_OFFSET 220 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; 221 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; 222#endif 223#endif 224 225 /* enable instruction cache now */ 226 icache_enable(); 227} 228 229/*initialize higher level parts of CPU like timers */ 230int cpu_init_r(void) 231{ 232 return (0); 233} 234 235void uart_port_conf(int port) 236{ 237 u32 *par = (u32 *) MMAP_PAR; 238 239 /* Setup Ports: */ 240 switch (port) { 241 case 1: 242 clrbits_be32(par, 0x00180000); 243 setbits_be32(par, 0x00180000); 244 break; 245 case 2: 246 clrbits_be32(par, 0x00000003); 247 clrbits_be32(par, 0xFFFFFFFC); 248 break; 249 } 250} 251#endif /* #if defined(CONFIG_M5253) */ 252 253#if defined(CONFIG_M5271) 254void cpu_init_f(void) 255{ 256#ifndef CONFIG_WATCHDOG 257 /* Disable the watchdog if we aren't using it */ 258 mbar_writeShort(MCF_WTM_WCR, 0); 259#endif 260 261 /* FlexBus Chipselect */ 262 init_fbcs(); 263 264#ifdef CONFIG_SYS_MCF_SYNCR 265 /* Set clockspeed according to board header file */ 266 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); 267#else 268 /* Set clockspeed to 100MHz */ 269 mbar_writeLong(MCF_FMPLL_SYNCR, 270 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); 271#endif 272 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ; 273} 274 275/* 276 * initialize higher level parts of CPU like timers 277 */ 278int cpu_init_r(void) 279{ 280 return (0); 281} 282 283void uart_port_conf(int port) 284{ 285 u16 temp; 286 287 /* Setup Ports: */ 288 switch (port) { 289 case 0: 290 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; 291 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); 292 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 293 break; 294 case 1: 295 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; 296 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); 297 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 298 break; 299 case 2: 300 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; 301 temp |= (0x3000); 302 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 303 break; 304 } 305} 306 307#if defined(CONFIG_CMD_NET) 308int fecpin_setclear(fec_info_t *info, int setclear) 309{ 310 if (setclear) { 311 /* Enable Ethernet pins */ 312 mbar_writeByte(MCF_GPIO_PAR_FECI2C, 313 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); 314 } else { 315 } 316 317 return 0; 318} 319#endif /* CONFIG_CMD_NET */ 320 321#endif /* CONFIG_M5271 */ 322 323#if defined(CONFIG_M5272) 324/* 325 * Breath some life into the CPU... 326 * 327 * Set up the memory map, 328 * initialize a bunch of registers, 329 * initialize the UPM's 330 */ 331void cpu_init_f(void) 332{ 333 /* if we come from RAM we assume the CPU is 334 * already initialized. 335 */ 336#ifndef CONFIG_MONITOR_IS_IN_RAM 337 sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR); 338 gpio_t *gpio = (gpio_t *) (MMAP_GPIO); 339 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); 340 341 out_be16(&sysctrl->sc_scr, CFG_SYS_SCR); 342 out_be16(&sysctrl->sc_spr, CFG_SYS_SPR); 343 344 /* Setup Ports: */ 345 out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT); 346 out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR); 347 out_be16(&gpio->gpio_padat, CFG_SYS_PADAT); 348 out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT); 349 out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR); 350 out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT); 351 out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT); 352 353 /* Memory Controller: */ 354 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); 355 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM); 356 357#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) 358 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM); 359 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM); 360#endif 361 362#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 363 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM); 364 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM); 365#endif 366 367#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 368 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM); 369 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM); 370#endif 371 372#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) 373 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM); 374 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM); 375#endif 376 377#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) 378 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM); 379 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM); 380#endif 381 382#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) 383 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM); 384 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM); 385#endif 386 387#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) 388 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM); 389 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM); 390#endif 391 392#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 393 394 /* enable instruction cache now */ 395 icache_enable(); 396 397} 398 399/* 400 * initialize higher level parts of CPU like timers 401 */ 402int cpu_init_r(void) 403{ 404 return (0); 405} 406 407void uart_port_conf(int port) 408{ 409 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 410 411 /* Setup Ports: */ 412 switch (port) { 413 case 0: 414 clrbits_be32(&gpio->gpio_pbcnt, 415 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); 416 setbits_be32(&gpio->gpio_pbcnt, 417 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); 418 break; 419 case 1: 420 clrbits_be32(&gpio->gpio_pdcnt, 421 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); 422 setbits_be32(&gpio->gpio_pdcnt, 423 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); 424 break; 425 } 426} 427 428#if defined(CONFIG_CMD_NET) 429int fecpin_setclear(fec_info_t *info, int setclear) 430{ 431 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 432 433 if (setclear) { 434 setbits_be32(&gpio->gpio_pbcnt, 435 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | 436 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | 437 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | 438 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3); 439 } else { 440 } 441 return 0; 442} 443#endif /* CONFIG_CMD_NET */ 444#endif /* #if defined(CONFIG_M5272) */ 445 446#if defined(CONFIG_M5275) 447 448/* 449 * Breathe some life into the CPU... 450 * 451 * Set up the memory map, 452 * initialize a bunch of registers, 453 * initialize the UPM's 454 */ 455void cpu_init_f(void) 456{ 457 /* 458 * if we come from RAM we assume the CPU is 459 * already initialized. 460 */ 461 462#ifndef CONFIG_MONITOR_IS_IN_RAM 463 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); 464 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); 465 466 /* Kill watchdog so we can initialize the PLL */ 467 out_be16(&wdog_reg->wcr, 0); 468 469 /* FlexBus Chipselect */ 470 init_fbcs(); 471#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 472 473#ifdef CONFIG_SYS_I2C_FSL 474 CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; 475 CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; 476#endif 477 478 /* enable instruction cache now */ 479 icache_enable(); 480} 481 482/* 483 * initialize higher level parts of CPU like timers 484 */ 485int cpu_init_r(void) 486{ 487 return (0); 488} 489 490void uart_port_conf(int port) 491{ 492 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 493 494 /* Setup Ports: */ 495 switch (port) { 496 case 0: 497 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); 498 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); 499 break; 500 case 1: 501 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); 502 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); 503 break; 504 case 2: 505 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); 506 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); 507 break; 508 } 509} 510 511#if defined(CONFIG_CMD_NET) 512int fecpin_setclear(fec_info_t *info, int setclear) 513{ 514 gpio_t *gpio = (gpio_t *)MMAP_GPIO; 515 u32 fec0_base; 516 517 if (fec_get_base_addr(0, &fec0_base)) 518 return -1; 519 520 if (setclear) { 521 /* Enable Ethernet pins */ 522 if (info->iobase == fec0_base) { 523 setbits_be16(&gpio->par_feci2c, 0x0f00); 524 setbits_8(&gpio->par_fec0hl, 0xc0); 525 } else { 526 setbits_be16(&gpio->par_feci2c, 0x00a0); 527 setbits_8(&gpio->par_fec1hl, 0xc0); 528 } 529 } else { 530 if (info->iobase == fec0_base) { 531 clrbits_be16(&gpio->par_feci2c, 0x0f00); 532 clrbits_8(&gpio->par_fec0hl, 0xc0); 533 } else { 534 clrbits_be16(&gpio->par_feci2c, 0x00a0); 535 clrbits_8(&gpio->par_fec1hl, 0xc0); 536 } 537 } 538 539 return 0; 540} 541#endif /* CONFIG_CMD_NET */ 542#endif /* #if defined(CONFIG_M5275) */ 543 544#if defined(CONFIG_M5282) 545/* 546 * Breath some life into the CPU... 547 * 548 * Set up the memory map, 549 * initialize a bunch of registers, 550 * initialize the UPM's 551 */ 552void cpu_init_f(void) 553{ 554#ifndef CONFIG_WATCHDOG 555 /* disable watchdog if we aren't using it */ 556 MCFWTM_WCR = 0; 557#endif 558 559#ifndef CONFIG_MONITOR_IS_IN_RAM 560 /* Set speed /PLL */ 561 MCFCLOCK_SYNCR = 562 MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) | 563 MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD); 564 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; 565 566 MCFGPIO_PBCDPAR = 0xc0; 567 568 /* Set up the GPIO ports */ 569#ifdef CONFIG_SYS_PEPAR 570 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; 571#endif 572#ifdef CONFIG_SYS_PFPAR 573 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; 574#endif 575#ifdef CFG_SYS_PJPAR 576 MCFGPIO_PJPAR = CFG_SYS_PJPAR; 577#endif 578#ifdef CONFIG_SYS_PSDPAR 579 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; 580#endif 581#ifdef CFG_SYS_PASPAR 582 MCFGPIO_PASPAR = CFG_SYS_PASPAR; 583#endif 584#ifdef CFG_SYS_PEHLPAR 585 MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; 586#endif 587#ifdef CONFIG_SYS_PQSPAR 588 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; 589#endif 590#ifdef CONFIG_SYS_PTCPAR 591 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; 592#endif 593#if defined(CONFIG_SYS_PORTTC) 594 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; 595#endif 596#if defined(CONFIG_SYS_DDRTC) 597 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; 598#endif 599#ifdef CONFIG_SYS_PTDPAR 600 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; 601#endif 602#ifdef CFG_SYS_PUAPAR 603 MCFGPIO_PUAPAR = CFG_SYS_PUAPAR; 604#endif 605 606#if defined(CONFIG_SYS_DDRD) 607 MCFGPIO_DDRD = CONFIG_SYS_DDRD; 608#endif 609#ifdef CFG_SYS_DDRUA 610 MCFGPIO_DDRUA = CFG_SYS_DDRUA; 611#endif 612 613 /* FlexBus Chipselect */ 614 init_fbcs(); 615 616#endif /* CONFIG_MONITOR_IS_IN_RAM */ 617 618 /* defer enabling cache until boot (see do_go) */ 619 /* icache_enable(); */ 620} 621 622/* 623 * initialize higher level parts of CPU like timers 624 */ 625int cpu_init_r(void) 626{ 627 return (0); 628} 629 630void uart_port_conf(int port) 631{ 632 /* Setup Ports: */ 633 switch (port) { 634 case 0: 635 MCFGPIO_PUAPAR &= 0xFc; 636 MCFGPIO_PUAPAR |= 0x03; 637 break; 638 case 1: 639 MCFGPIO_PUAPAR &= 0xF3; 640 MCFGPIO_PUAPAR |= 0x0C; 641 break; 642 case 2: 643 MCFGPIO_PASPAR &= 0xFF0F; 644 MCFGPIO_PASPAR |= 0x00A0; 645 break; 646 } 647} 648 649#if defined(CONFIG_CMD_NET) 650int fecpin_setclear(fec_info_t *info, int setclear) 651{ 652 if (setclear) { 653 MCFGPIO_PASPAR |= 0x0F00; 654 MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; 655 } else { 656 MCFGPIO_PASPAR &= 0xF0FF; 657 MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR; 658 } 659 return 0; 660} 661#endif /* CONFIG_CMD_NET */ 662#endif 663 664#if defined(CONFIG_M5249) 665/* 666 * Breath some life into the CPU... 667 * 668 * Set up the memory map, 669 * initialize a bunch of registers, 670 * initialize the UPM's 671 */ 672void cpu_init_f(void) 673{ 674 /* 675 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins 676 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins 677 * which is their primary function. 678 * ~Jeremy 679 */ 680 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC); 681 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC); 682 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN); 683 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN); 684 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT); 685 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT); 686 687 /* 688 * dBug Compliance: 689 * You can verify these values by using dBug's 'ird' 690 * (Internal Register Display) command 691 * ~Jeremy 692 * 693 */ 694 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ 695 mbar_writeByte(MCFSIM_SYPCR, 0x00); 696 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 697 mbar_writeByte(MCFSIM_SWSR, 0x00); 698 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); 699 mbar_writeByte(MCFSIM_SWDICR, 0x00); 700 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 701 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 702 mbar_writeByte(MCFSIM_I2CICR, 0x00); 703 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 704 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 705 mbar_writeByte(MCFSIM_ICR6, 0x00); 706 mbar_writeByte(MCFSIM_ICR7, 0x00); 707 mbar_writeByte(MCFSIM_ICR8, 0x00); 708 mbar_writeByte(MCFSIM_ICR9, 0x00); 709 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 710 711 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 712 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 713 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 714 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ 715 716 /* Setup interrupt priorities for gpio7 */ 717 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ 718 719 /* IDE Config registers */ 720 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); 721 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); 722 723 /* FlexBus Chipselect */ 724 init_fbcs(); 725 726 /* enable instruction cache now */ 727 icache_enable(); 728} 729 730/* 731 * initialize higher level parts of CPU like timers 732 */ 733int cpu_init_r(void) 734{ 735 return (0); 736} 737 738void uart_port_conf(int port) 739{ 740} 741#endif /* #if defined(CONFIG_M5249) */ 742