1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2003 4 * Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * MCF5282 additionals 7 * (C) Copyright 2005 8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 9 * 10 * MCF5275 additions 11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 12 * 13 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. 14 */ 15 16#include <init.h> 17#include <net.h> 18#include <vsprintf.h> 19#include <command.h> 20#include <asm/global_data.h> 21#include <asm/immap.h> 22#include <asm/io.h> 23#include <netdev.h> 24#include <linux/delay.h> 25#include "cpu.h" 26 27DECLARE_GLOBAL_DATA_PTR; 28 29#ifdef CONFIG_M5208 30int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 31{ 32 rcm_t *rcm = (rcm_t *)(MMAP_RCM); 33 34 udelay(1000); 35 36 out_8(&rcm->rcr, RCM_RCR_SOFTRST); 37 38 /* we don't return! */ 39 return 0; 40}; 41 42#if defined(CONFIG_DISPLAY_CPUINFO) 43int print_cpuinfo(void) 44{ 45 char buf1[32], buf2[32]; 46 47 printf("CPU: Freescale Coldfire MCF5208\n" 48 " CPU CLK %s MHz BUS CLK %s MHz\n", 49 strmhz(buf1, gd->cpu_clk), 50 strmhz(buf2, gd->bus_clk)); 51 return 0; 52}; 53#endif /* CONFIG_DISPLAY_CPUINFO */ 54#endif /* #ifdef CONFIG_M5208 */ 55 56#ifdef CONFIG_M5271 57#if defined(CONFIG_DISPLAY_CPUINFO) 58/* 59 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to 60 * determine which one we are running on, based on the Chip Identification 61 * Register (CIR). 62 */ 63int print_cpuinfo(void) 64{ 65 char buf[32]; 66 unsigned short cir; /* Chip Identification Register */ 67 unsigned short pin; /* Part identification number */ 68 unsigned char prn; /* Part revision number */ 69 char *cpu_model; 70 71 cir = mbar_readShort(MCF_CCM_CIR); 72 pin = cir >> MCF_CCM_CIR_PIN_LEN; 73 prn = cir & MCF_CCM_CIR_PRN_MASK; 74 75 switch (pin) { 76 case MCF_CCM_CIR_PIN_MCF5270: 77 cpu_model = "5270"; 78 break; 79 case MCF_CCM_CIR_PIN_MCF5271: 80 cpu_model = "5271"; 81 break; 82 default: 83 cpu_model = NULL; 84 break; 85 } 86 87 if (cpu_model) 88 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", 89 cpu_model, prn, strmhz(buf, CFG_SYS_CLK)); 90 else 91 printf("CPU: Unknown - Freescale ColdFire MCF5271 family" 92 " (PIN: 0x%x) rev. %hu, at %s MHz\n", 93 pin, prn, strmhz(buf, CFG_SYS_CLK)); 94 95 return 0; 96} 97#endif /* CONFIG_DISPLAY_CPUINFO */ 98 99int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 100{ 101 /* Call the board specific reset actions first. */ 102 if(board_reset) { 103 board_reset(); 104 } 105 106 mbar_writeByte(MCF_RCM_RCR, 107 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); 108 return 0; 109}; 110 111#if defined(CONFIG_WATCHDOG) 112void watchdog_reset(void) 113{ 114 mbar_writeShort(MCF_WTM_WSR, 0x5555); 115 mbar_writeShort(MCF_WTM_WSR, 0xAAAA); 116} 117 118int watchdog_disable(void) 119{ 120 mbar_writeShort(MCF_WTM_WCR, 0); 121 return (0); 122} 123 124int watchdog_init(void) 125{ 126 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); 127 return (0); 128} 129#endif /* #ifdef CONFIG_WATCHDOG */ 130 131#endif 132 133#ifdef CONFIG_M5272 134int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 135{ 136 wdog_t *wdp = (wdog_t *) (MMAP_WDOG); 137 138 out_be16(&wdp->wdog_wrrr, 0); 139 udelay(1000); 140 141 /* enable watchdog, set timeout to 0 and wait */ 142 out_be16(&wdp->wdog_wrrr, 1); 143 while (1) ; 144 145 /* we don't return! */ 146 return 0; 147}; 148 149#if defined(CONFIG_DISPLAY_CPUINFO) 150int print_cpuinfo(void) 151{ 152 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); 153 uchar msk; 154 char *suf; 155 156 puts("CPU: "); 157 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf; 158 switch (msk) { 159 case 0x2: 160 suf = "1K75N"; 161 break; 162 case 0x4: 163 suf = "3K75N"; 164 break; 165 default: 166 suf = NULL; 167 printf("Freescale MCF5272 (Mask:%01x)\n", msk); 168 break; 169 } 170 171 if (suf) 172 printf("Freescale MCF5272 %s\n", suf); 173 return 0; 174}; 175#endif /* CONFIG_DISPLAY_CPUINFO */ 176 177#if defined(CONFIG_WATCHDOG) 178/* Called by macro WATCHDOG_RESET */ 179void watchdog_reset(void) 180{ 181 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 182 183 out_be16(&wdt->wdog_wcr, 0); 184} 185 186int watchdog_disable(void) 187{ 188 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 189 190 /* reset watchdog counter */ 191 out_be16(&wdt->wdog_wcr, 0); 192 /* disable watchdog interrupt */ 193 out_be16(&wdt->wdog_wirr, 0); 194 /* disable watchdog timer */ 195 out_be16(&wdt->wdog_wrrr, 0); 196 197 puts("WATCHDOG:disabled\n"); 198 return (0); 199} 200 201int watchdog_init(void) 202{ 203 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 204 205 /* disable watchdog interrupt */ 206 out_be16(&wdt->wdog_wirr, 0); 207 208 /* set timeout and enable watchdog */ 209 out_be16(&wdt->wdog_wrrr, 210 (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 211 212 /* reset watchdog counter */ 213 out_be16(&wdt->wdog_wcr, 0); 214 215 puts("WATCHDOG:enabled\n"); 216 return (0); 217} 218#endif /* #ifdef CONFIG_WATCHDOG */ 219 220#endif /* #ifdef CONFIG_M5272 */ 221 222#ifdef CONFIG_M5275 223int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 224{ 225 rcm_t *rcm = (rcm_t *)(MMAP_RCM); 226 227 udelay(1000); 228 229 out_8(&rcm->rcr, RCM_RCR_SOFTRST); 230 231 /* we don't return! */ 232 return 0; 233}; 234 235#if defined(CONFIG_DISPLAY_CPUINFO) 236int print_cpuinfo(void) 237{ 238 char buf[32]; 239 240 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", 241 strmhz(buf, CFG_SYS_CLK)); 242 return 0; 243}; 244#endif /* CONFIG_DISPLAY_CPUINFO */ 245 246#if defined(CONFIG_WATCHDOG) 247/* Called by macro WATCHDOG_RESET */ 248void watchdog_reset(void) 249{ 250 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 251 252 out_be16(&wdt->wsr, 0x5555); 253 out_be16(&wdt->wsr, 0xaaaa); 254} 255 256int watchdog_disable(void) 257{ 258 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 259 260 /* reset watchdog counter */ 261 out_be16(&wdt->wsr, 0x5555); 262 out_be16(&wdt->wsr, 0xaaaa); 263 264 /* disable watchdog timer */ 265 out_be16(&wdt->wcr, 0); 266 267 puts("WATCHDOG:disabled\n"); 268 return (0); 269} 270 271int watchdog_init(void) 272{ 273 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 274 275 /* disable watchdog */ 276 out_be16(&wdt->wcr, 0); 277 278 /* set timeout and enable watchdog */ 279 out_be16(&wdt->wmr, 280 (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 281 282 /* reset watchdog counter */ 283 out_be16(&wdt->wsr, 0x5555); 284 out_be16(&wdt->wsr, 0xaaaa); 285 286 puts("WATCHDOG:enabled\n"); 287 return (0); 288} 289#endif /* #ifdef CONFIG_WATCHDOG */ 290 291#endif /* #ifdef CONFIG_M5275 */ 292 293#ifdef CONFIG_M5282 294#if defined(CONFIG_DISPLAY_CPUINFO) 295int print_cpuinfo(void) 296{ 297 unsigned char resetsource = MCFRESET_RSR; 298 299 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", 300 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); 301 printf("Reset:%s%s%s%s%s%s%s\n", 302 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", 303 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", 304 (resetsource & MCFRESET_RSR_EXT) ? " External" : "", 305 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", 306 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", 307 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", 308 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); 309 return 0; 310} 311#endif /* CONFIG_DISPLAY_CPUINFO */ 312 313int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 314{ 315 MCFRESET_RCR = MCFRESET_RCR_SOFTRST; 316 return 0; 317}; 318#endif 319 320#ifdef CONFIG_M5249 321#if defined(CONFIG_DISPLAY_CPUINFO) 322int print_cpuinfo(void) 323{ 324 char buf[32]; 325 326 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", 327 strmhz(buf, CFG_SYS_CLK)); 328 return 0; 329} 330#endif /* CONFIG_DISPLAY_CPUINFO */ 331 332int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 333{ 334 /* enable watchdog, set timeout to 0 and wait */ 335 mbar_writeByte(MCFSIM_SYPCR, 0xc0); 336 while (1) ; 337 338 /* we don't return! */ 339 return 0; 340}; 341#endif 342 343#ifdef CONFIG_M5253 344#if defined(CONFIG_DISPLAY_CPUINFO) 345int print_cpuinfo(void) 346{ 347 char buf[32]; 348 349 unsigned char resetsource = mbar_readLong(SIM_RSR); 350 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", 351 strmhz(buf, CFG_SYS_CLK)); 352 353 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { 354 printf("Reset:%s%s\n", 355 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" 356 : "", 357 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : 358 ""); 359 } 360 return 0; 361} 362#endif /* CONFIG_DISPLAY_CPUINFO */ 363 364int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 365{ 366 /* enable watchdog, set timeout to 0 and wait */ 367 mbar_writeByte(SIM_SYPCR, 0xc0); 368 while (1) ; 369 370 /* we don't return! */ 371 return 0; 372}; 373#endif 374 375#if defined(CONFIG_MCFFEC) 376/* Default initializations for MCFFEC controllers. To override, 377 * create a board-specific function called: 378 * int board_eth_init(struct bd_info *bis) 379 */ 380 381int cpu_eth_init(struct bd_info *bis) 382{ 383 return mcffec_initialize(bis); 384} 385#endif 386