1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@amd.com>
5 */
6
7#include <common.h>
8#include <init.h>
9#include <time.h>
10#include <asm/arch/hardware.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/armv8/mmu.h>
13#include <asm/cache.h>
14#include <asm/global_data.h>
15#include <asm/io.h>
16#include <zynqmp_firmware.h>
17#include <asm/cache.h>
18#include <dm/platdata.h>
19
20#define ZYNQ_SILICON_VER_MASK	0xF000
21#define ZYNQ_SILICON_VER_SHIFT	12
22
23DECLARE_GLOBAL_DATA_PTR;
24
25/*
26 * Number of filled static entries and also the first empty
27 * slot in zynqmp_mem_map.
28 */
29#define ZYNQMP_MEM_MAP_USED	4
30
31#if !defined(CONFIG_ZYNQMP_NO_DDR)
32#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
33#else
34#define DRAM_BANKS 0
35#endif
36
37#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
38#define TCM_MAP 1
39#else
40#define TCM_MAP 0
41#endif
42
43/* +1 is end of list which needs to be empty */
44#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
45
46static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
47	{
48		.virt = 0x80000000UL,
49		.phys = 0x80000000UL,
50		.size = 0x70000000UL,
51		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52			 PTE_BLOCK_NON_SHARE |
53			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
54	}, {
55		.virt = 0xf8000000UL,
56		.phys = 0xf8000000UL,
57		.size = 0x07e00000UL,
58		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
59			 PTE_BLOCK_NON_SHARE |
60			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
61	}, {
62		.virt = 0x400000000UL,
63		.phys = 0x400000000UL,
64		.size = 0x400000000UL,
65		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
66			 PTE_BLOCK_NON_SHARE |
67			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
68	}, {
69		.virt = 0x1000000000UL,
70		.phys = 0x1000000000UL,
71		.size = 0xf000000000UL,
72		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
73			 PTE_BLOCK_NON_SHARE |
74			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
75	}
76};
77
78void mem_map_fill(void)
79{
80	int banks = ZYNQMP_MEM_MAP_USED;
81
82#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
83	zynqmp_mem_map[banks].virt = 0xffe00000UL;
84	zynqmp_mem_map[banks].phys = 0xffe00000UL;
85	zynqmp_mem_map[banks].size = 0x00200000UL;
86	zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
87				      PTE_BLOCK_INNER_SHARE;
88	banks = banks + 1;
89#endif
90
91#if !defined(CONFIG_ZYNQMP_NO_DDR)
92	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
93		/* Zero size means no more DDR that's this is end */
94		if (!gd->bd->bi_dram[i].size)
95			break;
96
97		zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
98		zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
99		zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
100		zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
101					      PTE_BLOCK_INNER_SHARE;
102		banks = banks + 1;
103	}
104#endif
105}
106
107struct mm_region *mem_map = zynqmp_mem_map;
108
109u64 get_page_table_size(void)
110{
111	return 0x14000;
112}
113
114#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
115void tcm_init(u8 mode)
116{
117	puts("WARNING: Initializing TCM overwrites TCM content\n");
118	initialize_tcm(mode);
119	memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
120}
121#endif
122
123#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
124int arm_reserve_mmu(void)
125{
126	tcm_init(TCM_LOCK);
127	gd->arch.tlb_size = PGTABLE_SIZE;
128	gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
129
130	return 0;
131}
132#endif
133
134static unsigned int zynqmp_get_silicon_version_secure(void)
135{
136	u32 ver;
137
138	ver = readl(&csu_base->version);
139	ver &= ZYNQMP_SILICON_VER_MASK;
140	ver >>= ZYNQMP_SILICON_VER_SHIFT;
141
142	return ver;
143}
144
145unsigned int zynqmp_get_silicon_version(void)
146{
147	if (current_el() == 3)
148		return zynqmp_get_silicon_version_secure();
149
150	gd->cpu_clk = get_tbclk();
151
152	switch (gd->cpu_clk) {
153	case 50000000:
154		return ZYNQMP_CSU_VERSION_QEMU;
155	}
156
157	return ZYNQMP_CSU_VERSION_SILICON;
158}
159
160static int zynqmp_mmio_rawwrite(const u32 address,
161		      const u32 mask,
162		      const u32 value)
163{
164	u32 data;
165	u32 value_local = value;
166	int ret;
167
168	ret = zynqmp_mmio_read(address, &data);
169	if (ret)
170		return ret;
171
172	data &= ~mask;
173	value_local &= mask;
174	value_local |= data;
175	writel(value_local, (ulong)address);
176	return 0;
177}
178
179static int zynqmp_mmio_rawread(const u32 address, u32 *value)
180{
181	*value = readl((ulong)address);
182	return 0;
183}
184
185int zynqmp_mmio_write(const u32 address,
186		      const u32 mask,
187		      const u32 value)
188{
189	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
190		return zynqmp_mmio_rawwrite(address, mask, value);
191#if defined(CONFIG_ZYNQMP_FIRMWARE)
192	else
193		return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
194					 value, 0, NULL);
195#endif
196
197	return -EINVAL;
198}
199
200int zynqmp_mmio_read(const u32 address, u32 *value)
201{
202	u32 ret = -EINVAL;
203
204	if (!value)
205		return ret;
206
207	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
208		ret = zynqmp_mmio_rawread(address, value);
209	}
210#if defined(CONFIG_ZYNQMP_FIRMWARE)
211	else {
212		u32 ret_payload[PAYLOAD_ARG_CNT];
213
214		ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
215					0, ret_payload);
216		*value = ret_payload[1];
217	}
218#endif
219
220	return ret;
221}
222
223U_BOOT_DRVINFO(soc_xilinx_zynqmp) = {
224	.name = "soc_xilinx_zynqmp",
225};
226