1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 */ 5 6#include <common.h> 7#include <fdtdec.h> 8#include <log.h> 9#include <asm/io.h> 10#include <asm/arch-tegra/ap.h> 11#include <asm/arch-tegra/apb_misc.h> 12#include <asm/arch/clock.h> 13#include <asm/arch/emc.h> 14#include <asm/arch/tegra.h> 15 16/* 17 * The EMC registers have shadow registers. When the EMC clock is updated 18 * in the clock controller, the shadow registers are copied to the active 19 * registers, allowing glitchless memory bus frequency changes. 20 * This function updates the shadow registers for a new clock frequency, 21 * and relies on the clock lock on the emc clock to avoid races between 22 * multiple frequency changes 23 */ 24 25/* 26 * This table defines the ordering of the registers provided to 27 * tegra_set_mmc() 28 * TODO: Convert to fdt version once available 29 */ 30static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = { 31 0x2c, /* RC */ 32 0x30, /* RFC */ 33 0x34, /* RAS */ 34 0x38, /* RP */ 35 0x3c, /* R2W */ 36 0x40, /* W2R */ 37 0x44, /* R2P */ 38 0x48, /* W2P */ 39 0x4c, /* RD_RCD */ 40 0x50, /* WR_RCD */ 41 0x54, /* RRD */ 42 0x58, /* REXT */ 43 0x5c, /* WDV */ 44 0x60, /* QUSE */ 45 0x64, /* QRST */ 46 0x68, /* QSAFE */ 47 0x6c, /* RDV */ 48 0x70, /* REFRESH */ 49 0x74, /* BURST_REFRESH_NUM */ 50 0x78, /* PDEX2WR */ 51 0x7c, /* PDEX2RD */ 52 0x80, /* PCHG2PDEN */ 53 0x84, /* ACT2PDEN */ 54 0x88, /* AR2PDEN */ 55 0x8c, /* RW2PDEN */ 56 0x90, /* TXSR */ 57 0x94, /* TCKE */ 58 0x98, /* TFAW */ 59 0x9c, /* TRPAB */ 60 0xa0, /* TCLKSTABLE */ 61 0xa4, /* TCLKSTOP */ 62 0xa8, /* TREFBW */ 63 0xac, /* QUSE_EXTRA */ 64 0x114, /* FBIO_CFG6 */ 65 0xb0, /* ODT_WRITE */ 66 0xb4, /* ODT_READ */ 67 0x104, /* FBIO_CFG5 */ 68 0x2bc, /* CFG_DIG_DLL */ 69 0x2c0, /* DLL_XFORM_DQS */ 70 0x2c4, /* DLL_XFORM_QUSE */ 71 0x2e0, /* ZCAL_REF_CNT */ 72 0x2e4, /* ZCAL_WAIT_CNT */ 73 0x2a8, /* AUTO_CAL_INTERVAL */ 74 0x2d0, /* CFG_CLKTRIM_0 */ 75 0x2d4, /* CFG_CLKTRIM_1 */ 76 0x2d8, /* CFG_CLKTRIM_2 */ 77}; 78 79struct emc_ctlr *emc_get_controller(const void *blob) 80{ 81 fdt_addr_t addr; 82 int node; 83 84 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC); 85 if (node > 0) { 86 addr = fdtdec_get_addr(blob, node, "reg"); 87 if (addr != FDT_ADDR_T_NONE) 88 return (struct emc_ctlr *)addr; 89 } 90 return NULL; 91} 92 93/* Error codes we use */ 94enum { 95 ERR_NO_EMC_NODE = -10, 96 ERR_NO_EMC_REG, 97 ERR_NO_FREQ, 98 ERR_FREQ_NOT_FOUND, 99 ERR_BAD_REGS, 100 ERR_NO_RAM_CODE, 101 ERR_RAM_CODE_NOT_FOUND, 102}; 103 104/** 105 * Find EMC tables for the given ram code. 106 * 107 * The tegra EMC binding has two options, one using the ram code and one not. 108 * We detect which is in use by looking for the nvidia,use-ram-code property. 109 * If this is not present, then the EMC tables are directly below 'node', 110 * otherwise we select the correct emc-tables subnode based on the 'ram_code' 111 * value. 112 * 113 * @param blob Device tree blob 114 * @param node EMC node (nvidia,tegra20-emc compatible string) 115 * @param ram_code RAM code to select (0-3, or -1 if unknown) 116 * Return: 0 if ok, otherwise a -ve ERR_ code (see enum above) 117 */ 118static int find_emc_tables(const void *blob, int node, int ram_code) 119{ 120 int need_ram_code; 121 int depth; 122 int offset; 123 124 /* If we are using RAM codes, scan through the tables for our code */ 125 need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code"); 126 if (!need_ram_code) 127 return node; 128 if (ram_code == -1) { 129 debug("%s: RAM code required but not supplied\n", __func__); 130 return ERR_NO_RAM_CODE; 131 } 132 133 offset = node; 134 depth = 0; 135 do { 136 /* 137 * Sadly there is no compatible string so we cannot use 138 * fdtdec_next_compatible_subnode(). 139 */ 140 offset = fdt_next_node(blob, offset, &depth); 141 if (depth <= 0) 142 break; 143 144 /* Make sure this is a direct subnode */ 145 if (depth != 1) 146 continue; 147 if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL))) 148 continue; 149 150 if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1) 151 == ram_code) 152 return offset; 153 } while (1); 154 155 debug("%s: Could not find tables for RAM code %d\n", __func__, 156 ram_code); 157 return ERR_RAM_CODE_NOT_FOUND; 158} 159 160/** 161 * Decode the EMC node of the device tree, returning a pointer to the emc 162 * controller and the table to be used for the given rate. 163 * 164 * @param blob Device tree blob 165 * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) 166 * @param emcp Returns address of EMC controller registers 167 * @param tablep Returns pointer to table to program into EMC. There are 168 * TEGRA_EMC_NUM_REGS entries, destined for offsets as per the 169 * emc_reg_addr array. 170 * Return: 0 if ok, otherwise a -ve error code which will allow someone to 171 * figure out roughly what went wrong by looking at this code. 172 */ 173static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp, 174 const u32 **tablep) 175{ 176 struct apb_misc_pp_ctlr *pp = 177 (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; 178 int ram_code; 179 int depth; 180 int node; 181 182 ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK) 183 >> RAM_CODE_SHIFT; 184 /* 185 * The EMC clock rate is twice the bus rate, and the bus rate is 186 * measured in kHz 187 */ 188 rate = rate / 2 / 1000; 189 190 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC); 191 if (node < 0) { 192 debug("%s: No EMC node found in FDT\n", __func__); 193 return ERR_NO_EMC_NODE; 194 } 195 *emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg"); 196 if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) { 197 debug("%s: No EMC node reg property\n", __func__); 198 return ERR_NO_EMC_REG; 199 } 200 201 /* Work out the parent node which contains our EMC tables */ 202 node = find_emc_tables(blob, node, ram_code & 3); 203 if (node < 0) 204 return node; 205 206 depth = 0; 207 for (;;) { 208 int node_rate; 209 210 node = fdtdec_next_compatible_subnode(blob, node, 211 COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth); 212 if (node < 0) 213 break; 214 node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1); 215 if (node_rate == -1) { 216 debug("%s: Missing clock-frequency\n", __func__); 217 return ERR_NO_FREQ; /* we expect this property */ 218 } 219 220 if (node_rate == rate) 221 break; 222 } 223 if (node < 0) { 224 debug("%s: No node found for clock frequency %d\n", __func__, 225 rate); 226 return ERR_FREQ_NOT_FOUND; 227 } 228 229 *tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers", 230 TEGRA_EMC_NUM_REGS); 231 if (!*tablep) { 232 debug("%s: node '%s' array missing / wrong size\n", __func__, 233 fdt_get_name(blob, node, NULL)); 234 return ERR_BAD_REGS; 235 } 236 237 /* All seems well */ 238 return 0; 239} 240 241int tegra_set_emc(const void *blob, unsigned rate) 242{ 243 struct emc_ctlr *emc; 244 const u32 *table = NULL; 245 int err, i; 246 247 err = decode_emc(blob, rate, &emc, &table); 248 if (err) { 249 debug("Warning: no valid EMC (%d), memory timings unset\n", 250 err); 251 return err; 252 } 253 254 debug("%s: Table found, setting EMC values as follows:\n", __func__); 255 for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) { 256 u32 value = fdt32_to_cpu(table[i]); 257 u32 addr = (uintptr_t)emc + emc_reg_addr[i]; 258 259 debug(" %#x: %#x\n", addr, value); 260 writel(value, addr); 261 } 262 263 /* trigger emc with new settings */ 264 clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY, 265 clock_get_rate(CLOCK_ID_MEMORY), NULL); 266 debug("EMC clock set to %lu\n", 267 clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY)); 268 269 return 0; 270} 271