1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2010-2015 5 * NVIDIA Corporation <www.nvidia.com> 6 */ 7 8/* Tegra20 Clock control functions */ 9 10#include <common.h> 11#include <errno.h> 12#include <init.h> 13#include <log.h> 14#include <asm/io.h> 15#include <asm/arch/clock.h> 16#include <asm/arch/tegra.h> 17#include <asm/arch-tegra/clk_rst.h> 18#include <asm/arch-tegra/timer.h> 19#include <div64.h> 20#include <fdtdec.h> 21#include <linux/delay.h> 22#include <linux/printk.h> 23 24#include <dt-bindings/clock/tegra20-car.h> 25 26/* 27 * Clock types that we can use as a source. The Tegra20 has muxes for the 28 * peripheral clocks, and in most cases there are four options for the clock 29 * source. This gives us a clock 'type' and exploits what commonality exists 30 * in the device. 31 * 32 * Letters are obvious, except for T which means CLK_M, and S which means the 33 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 34 * datasheet) and PLL_M are different things. The former is the basic 35 * clock supplied to the SOC from an external oscillator. The latter is the 36 * memory clock PLL. 37 * 38 * See definitions in clock_id in the header file. 39 */ 40enum clock_type_id { 41 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 42 CLOCK_TYPE_MCPA, /* and so on */ 43 CLOCK_TYPE_MCPT, 44 CLOCK_TYPE_PCM, 45 CLOCK_TYPE_PCMT, 46 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */ 47 CLOCK_TYPE_PCXTS, 48 CLOCK_TYPE_PDCT, 49 50 CLOCK_TYPE_COUNT, 51 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 52}; 53 54enum { 55 CLOCK_MAX_MUX = 4 /* number of source options for each clock */ 56}; 57 58/* 59 * Clock source mux for each clock type. This just converts our enum into 60 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS 61 * is special as it has 5 sources. Since it also has a different number of 62 * bits in its register for the source, we just handle it with a special 63 * case in the code. 64 */ 65#define CLK(x) CLOCK_ID_ ## x 66static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = { 67 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) }, 68 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) }, 69 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) }, 70 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) }, 71 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, 72 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, 73 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) }, 74 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) }, 75}; 76 77/* 78 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is 79 * not in the header file since it is for purely internal use - we want 80 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid 81 * confusion bewteen PERIPH_ID_... and PERIPHC_... 82 * 83 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be 84 * confusing. 85 * 86 * Note to SOC vendors: perhaps define a unified numbering for peripherals and 87 * use it for reset, clock enable, clock source/divider and even pinmuxing 88 * if you can. 89 */ 90enum periphc_internal_id { 91 /* 0x00 */ 92 PERIPHC_I2S1, 93 PERIPHC_I2S2, 94 PERIPHC_SPDIF_OUT, 95 PERIPHC_SPDIF_IN, 96 PERIPHC_PWM, 97 PERIPHC_SPI1, 98 PERIPHC_SPI2, 99 PERIPHC_SPI3, 100 101 /* 0x08 */ 102 PERIPHC_XIO, 103 PERIPHC_I2C1, 104 PERIPHC_DVC_I2C, 105 PERIPHC_TWC, 106 PERIPHC_0c, 107 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */ 108 PERIPHC_DISP1, 109 PERIPHC_DISP2, 110 111 /* 0x10 */ 112 PERIPHC_CVE, 113 PERIPHC_IDE0, 114 PERIPHC_VI, 115 PERIPHC_1c, 116 PERIPHC_SDMMC1, 117 PERIPHC_SDMMC2, 118 PERIPHC_G3D, 119 PERIPHC_G2D, 120 121 /* 0x18 */ 122 PERIPHC_NDFLASH, 123 PERIPHC_SDMMC4, 124 PERIPHC_VFIR, 125 PERIPHC_EPP, 126 PERIPHC_MPE, 127 PERIPHC_MIPI, 128 PERIPHC_UART1, 129 PERIPHC_UART2, 130 131 /* 0x20 */ 132 PERIPHC_HOST1X, 133 PERIPHC_21, 134 PERIPHC_TVO, 135 PERIPHC_HDMI, 136 PERIPHC_24, 137 PERIPHC_TVDAC, 138 PERIPHC_I2C2, 139 PERIPHC_EMC, 140 141 /* 0x28 */ 142 PERIPHC_UART3, 143 PERIPHC_29, 144 PERIPHC_VI_SENSOR, 145 PERIPHC_2b, 146 PERIPHC_2c, 147 PERIPHC_SPI4, 148 PERIPHC_I2C3, 149 PERIPHC_SDMMC3, 150 151 /* 0x30 */ 152 PERIPHC_UART4, 153 PERIPHC_UART5, 154 PERIPHC_VDE, 155 PERIPHC_OWR, 156 PERIPHC_NOR, 157 PERIPHC_CSITE, 158 159 PERIPHC_COUNT, 160 161 PERIPHC_NONE = -1, 162}; 163 164/* 165 * Clock type for each peripheral clock source. We put the name in each 166 * record just so it is easy to match things up 167 */ 168#define TYPE(name, type) type 169static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 170 /* 0x00 */ 171 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 172 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 173 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 174 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), 175 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS), 176 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT), 177 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT), 178 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT), 179 180 /* 0x08 */ 181 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT), 182 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), 183 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16), 184 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT), 185 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 186 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT), 187 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT), 188 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT), 189 190 /* 0x10 */ 191 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), 192 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT), 193 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 194 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 195 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), 196 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), 197 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), 198 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), 199 200 /* 0x18 */ 201 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), 202 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), 203 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), 204 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), 205 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), 206 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), 207 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), 208 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), 209 210 /* 0x20 */ 211 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), 212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 213 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), 214 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT), 215 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 216 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), 217 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), 218 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), 219 220 /* 0x28 */ 221 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), 222 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 223 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), 224 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 225 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), 226 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT), 227 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), 228 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), 229 230 /* 0x30 */ 231 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), 232 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), 233 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), 234 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), 235 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), 236 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), 237}; 238 239/* 240 * This array translates a periph_id to a periphc_internal_id 241 * 242 * Not present/matched up: 243 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 244 * SPDIF - which is both 0x08 and 0x0c 245 * 246 */ 247#define NONE(name) (-1) 248#define OFFSET(name, value) PERIPHC_ ## name 249static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 250 /* Low word: 31:0 */ 251 NONE(CPU), 252 NONE(RESERVED1), 253 NONE(RESERVED2), 254 NONE(AC97), 255 NONE(RTC), 256 NONE(TMR), 257 PERIPHC_UART1, 258 PERIPHC_UART2, /* and vfir 0x68 */ 259 260 /* 0x08 */ 261 NONE(GPIO), 262 PERIPHC_SDMMC2, 263 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ 264 PERIPHC_I2S1, 265 PERIPHC_I2C1, 266 PERIPHC_NDFLASH, 267 PERIPHC_SDMMC1, 268 PERIPHC_SDMMC4, 269 270 /* 0x10 */ 271 PERIPHC_TWC, 272 PERIPHC_PWM, 273 PERIPHC_I2S2, 274 PERIPHC_EPP, 275 PERIPHC_VI, 276 PERIPHC_G2D, 277 NONE(USBD), 278 NONE(ISP), 279 280 /* 0x18 */ 281 PERIPHC_G3D, 282 PERIPHC_IDE0, 283 PERIPHC_DISP2, 284 PERIPHC_DISP1, 285 PERIPHC_HOST1X, 286 NONE(VCP), 287 NONE(RESERVED30), 288 NONE(CACHE2), 289 290 /* Middle word: 63:32 */ 291 NONE(MEM), 292 NONE(AHBDMA), 293 NONE(APBDMA), 294 NONE(RESERVED35), 295 NONE(KBC), 296 NONE(STAT_MON), 297 NONE(PMC), 298 NONE(FUSE), 299 300 /* 0x28 */ 301 NONE(KFUSE), 302 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */ 303 PERIPHC_NOR, 304 PERIPHC_SPI1, 305 PERIPHC_SPI2, 306 PERIPHC_XIO, 307 PERIPHC_SPI3, 308 PERIPHC_DVC_I2C, 309 310 /* 0x30 */ 311 NONE(DSI), 312 PERIPHC_TVO, /* also CVE 0x40 */ 313 PERIPHC_MIPI, 314 PERIPHC_HDMI, 315 PERIPHC_CSITE, 316 PERIPHC_TVDAC, 317 PERIPHC_I2C2, 318 PERIPHC_UART3, 319 320 /* 0x38 */ 321 NONE(RESERVED56), 322 PERIPHC_EMC, 323 NONE(USB2), 324 NONE(USB3), 325 PERIPHC_MPE, 326 PERIPHC_VDE, 327 NONE(BSEA), 328 NONE(BSEV), 329 330 /* Upper word 95:64 */ 331 NONE(SPEEDO), 332 PERIPHC_UART4, 333 PERIPHC_UART5, 334 PERIPHC_I2C3, 335 PERIPHC_SPI4, 336 PERIPHC_SDMMC3, 337 NONE(PCIE), 338 PERIPHC_OWR, 339 340 /* 0x48 */ 341 NONE(AFI), 342 NONE(CORESIGHT), 343 NONE(PCIEXCLK), 344 NONE(AVPUCQ), 345 NONE(RESERVED76), 346 NONE(RESERVED77), 347 NONE(RESERVED78), 348 NONE(RESERVED79), 349 350 /* 0x50 */ 351 NONE(RESERVED80), 352 NONE(RESERVED81), 353 NONE(RESERVED82), 354 NONE(RESERVED83), 355 NONE(IRAMA), 356 NONE(IRAMB), 357 NONE(IRAMC), 358 NONE(IRAMD), 359 360 /* 0x58 */ 361 NONE(CRAM2), 362}; 363 364/* 365 * PLL divider shift/mask tables for all PLL IDs. 366 */ 367struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 368 /* 369 * T20 and T25 370 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) 371 * If lock_ena or lock_det are >31, they're not used in that PLL. 372 */ 373 374 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, 375 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ 376 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, 377 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 378 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 379 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ 380 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 381 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ 382 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, 383 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ 384 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 385 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ 386 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, 387 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ 388 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 389 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 390 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 391 .lock_ena = 18, .lock_det = 0, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS */ 392}; 393 394/* 395 * Get the oscillator frequency, from the corresponding hardware configuration 396 * field. T20 has 4 frequencies that it supports. 397 */ 398enum clock_osc_freq clock_get_osc_freq(void) 399{ 400 struct clk_rst_ctlr *clkrst = 401 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 402 u32 reg; 403 404 reg = readl(&clkrst->crc_osc_ctrl); 405 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 406 407 return reg << 2; 408} 409 410/* Returns a pointer to the clock source register for a peripheral */ 411u32 *get_periph_source_reg(enum periph_id periph_id) 412{ 413 struct clk_rst_ctlr *clkrst = 414 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 415 enum periphc_internal_id internal_id; 416 417 assert(clock_periph_id_isvalid(periph_id)); 418 internal_id = periph_id_to_internal_id[periph_id]; 419 assert(internal_id != -1); 420 return &clkrst->crc_clk_src[internal_id]; 421} 422 423int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 424 int *divider_bits, int *type) 425{ 426 enum periphc_internal_id internal_id; 427 428 if (!clock_periph_id_isvalid(periph_id)) 429 return -1; 430 431 internal_id = periph_id_to_internal_id[periph_id]; 432 if (!periphc_internal_id_isvalid(internal_id)) 433 return -1; 434 435 *type = clock_periph_type[internal_id]; 436 if (!clock_type_id_isvalid(*type)) 437 return -1; 438 439 /* 440 * Special cases here for the clock with a 4-bit source mux and I2C 441 * with its 16-bit divisor 442 */ 443 if (*type == CLOCK_TYPE_PCXTS) 444 *mux_bits = MASK_BITS_31_28; 445 else 446 *mux_bits = MASK_BITS_31_30; 447 if (*type == CLOCK_TYPE_PCMT16) 448 *divider_bits = 16; 449 else 450 *divider_bits = 8; 451 452 return 0; 453} 454 455enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) 456{ 457 enum periphc_internal_id internal_id; 458 int type; 459 460 if (!clock_periph_id_isvalid(periph_id)) 461 return CLOCK_ID_NONE; 462 463 internal_id = periph_id_to_internal_id[periph_id]; 464 if (!periphc_internal_id_isvalid(internal_id)) 465 return CLOCK_ID_NONE; 466 467 type = clock_periph_type[internal_id]; 468 if (!clock_type_id_isvalid(type)) 469 return CLOCK_ID_NONE; 470 471 return clock_source[type][source]; 472} 473 474/** 475 * Given a peripheral ID and the required source clock, this returns which 476 * value should be programmed into the source mux for that peripheral. 477 * 478 * There is special code here to handle the one source type with 5 sources. 479 * 480 * @param periph_id peripheral to start 481 * @param source PLL id of required parent clock 482 * @param mux_bits Set to number of bits in mux register: 2 or 4 483 * @param divider_bits Set to number of divider bits (8 or 16) 484 * Return: mux value (0-4, or -1 if not found) 485 */ 486int get_periph_clock_source(enum periph_id periph_id, 487 enum clock_id parent, int *mux_bits, int *divider_bits) 488{ 489 enum clock_type_id type; 490 int mux, err; 491 492 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); 493 assert(!err); 494 495 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 496 if (clock_source[type][mux] == parent) 497 return mux; 498 499 /* 500 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS 501 * which is not in our table. If not, then they are asking for a 502 * source which this peripheral can't access through its mux. 503 */ 504 assert(type == CLOCK_TYPE_PCXTS); 505 assert(parent == CLOCK_ID_SFROM32KHZ); 506 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ) 507 return 4; /* mux value for this clock */ 508 509 /* if we get here, either us or the caller has made a mistake */ 510 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 511 parent); 512 return -1; 513} 514 515void clock_set_enable(enum periph_id periph_id, int enable) 516{ 517 struct clk_rst_ctlr *clkrst = 518 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 519 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 520 u32 reg; 521 522 /* Enable/disable the clock to this peripheral */ 523 assert(clock_periph_id_isvalid(periph_id)); 524 reg = readl(clk); 525 if (enable) 526 reg |= PERIPH_MASK(periph_id); 527 else 528 reg &= ~PERIPH_MASK(periph_id); 529 writel(reg, clk); 530} 531 532void reset_set_enable(enum periph_id periph_id, int enable) 533{ 534 struct clk_rst_ctlr *clkrst = 535 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 536 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 537 u32 reg; 538 539 /* Enable/disable reset to the peripheral */ 540 assert(clock_periph_id_isvalid(periph_id)); 541 reg = readl(reset); 542 if (enable) 543 reg |= PERIPH_MASK(periph_id); 544 else 545 reg &= ~PERIPH_MASK(periph_id); 546 writel(reg, reset); 547} 548 549#if CONFIG_IS_ENABLED(OF_CONTROL) 550/* 551 * Convert a device tree clock ID to our peripheral ID. They are mostly 552 * the same but we are very cautious so we check that a valid clock ID is 553 * provided. 554 * 555 * @param clk_id Clock ID according to tegra20 device tree binding 556 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 557 */ 558enum periph_id clk_id_to_periph_id(int clk_id) 559{ 560 if (clk_id > PERIPH_ID_COUNT) 561 return PERIPH_ID_NONE; 562 563 switch (clk_id) { 564 case PERIPH_ID_RESERVED1: 565 case PERIPH_ID_RESERVED2: 566 case PERIPH_ID_RESERVED30: 567 case PERIPH_ID_RESERVED35: 568 case PERIPH_ID_RESERVED56: 569 case PERIPH_ID_PCIEXCLK: 570 case PERIPH_ID_RESERVED76: 571 case PERIPH_ID_RESERVED77: 572 case PERIPH_ID_RESERVED78: 573 case PERIPH_ID_RESERVED79: 574 case PERIPH_ID_RESERVED80: 575 case PERIPH_ID_RESERVED81: 576 case PERIPH_ID_RESERVED82: 577 case PERIPH_ID_RESERVED83: 578 case PERIPH_ID_RESERVED91: 579 return PERIPH_ID_NONE; 580 default: 581 return clk_id; 582 } 583} 584 585/* 586 * Convert a device tree clock ID to our PLL ID. 587 * 588 * @param clk_id Clock ID according to tegra20 device tree binding 589 * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid 590 */ 591enum clock_id clk_id_to_pll_id(int clk_id) 592{ 593 switch (clk_id) { 594 case TEGRA20_CLK_PLL_C: 595 return CLOCK_ID_CGENERAL; 596 case TEGRA20_CLK_PLL_M: 597 return CLOCK_ID_MEMORY; 598 case TEGRA20_CLK_PLL_P: 599 return CLOCK_ID_PERIPH; 600 case TEGRA20_CLK_PLL_A: 601 return CLOCK_ID_AUDIO; 602 case TEGRA20_CLK_PLL_U: 603 return CLOCK_ID_USB; 604 case TEGRA20_CLK_PLL_D: 605 case TEGRA20_CLK_PLL_D_OUT0: 606 return CLOCK_ID_DISPLAY; 607 case TEGRA20_CLK_PLL_X: 608 return CLOCK_ID_XCPU; 609 case TEGRA20_CLK_PLL_E: 610 return CLOCK_ID_EPCI; 611 case TEGRA20_CLK_CLK_32K: 612 return CLOCK_ID_32KHZ; 613 case TEGRA20_CLK_CLK_M: 614 return CLOCK_ID_CLK_M; 615 default: 616 return CLOCK_ID_NONE; 617 } 618} 619#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 620 621void clock_early_init(void) 622{ 623 /* 624 * PLLP output frequency set to 216MHz 625 * PLLC output frequency set to 600Mhz 626 * 627 * TODO: Can we calculate these values instead of hard-coding? 628 */ 629 switch (clock_get_osc_freq()) { 630 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 631 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8); 632 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 633 break; 634 635 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 636 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8); 637 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 638 break; 639 640 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 641 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8); 642 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 643 break; 644 case CLOCK_OSC_FREQ_19_2: 645 default: 646 /* 647 * These are not supported. It is too early to print a 648 * message and the UART likely won't work anyway due to the 649 * oscillator being wrong. 650 */ 651 break; 652 } 653} 654 655void arch_timer_init(void) 656{ 657} 658 659#define PMC_SATA_PWRGT 0x1ac 660#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) 661#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) 662 663#define PLLE_SS_CNTL 0x68 664#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) 665#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 666#define PLLE_SS_CNTL_SSCBYP (1 << 12) 667#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 668#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 669#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 670 671#define PLLE_BASE 0x0e8 672#define PLLE_BASE_ENABLE_CML (1 << 31) 673#define PLLE_BASE_ENABLE (1 << 30) 674#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 675#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) 676#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 677#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 678 679#define PLLE_MISC 0x0ec 680#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) 681#define PLLE_MISC_PLL_READY (1 << 15) 682#define PLLE_MISC_LOCK (1 << 11) 683#define PLLE_MISC_LOCK_ENABLE (1 << 9) 684#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) 685 686static int tegra_plle_train(void) 687{ 688 unsigned int timeout = 2000; 689 unsigned long value; 690 691 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 692 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; 693 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 694 695 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 696 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 697 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 698 699 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); 700 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; 701 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); 702 703 do { 704 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 705 if (value & PLLE_MISC_PLL_READY) 706 break; 707 708 udelay(100); 709 } while (--timeout); 710 711 if (timeout == 0) { 712 pr_err("timeout waiting for PLLE to become ready"); 713 return -ETIMEDOUT; 714 } 715 716 return 0; 717} 718 719int tegra_plle_enable(void) 720{ 721 unsigned int timeout = 1000; 722 u32 value; 723 int err; 724 725 /* disable PLLE clock */ 726 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 727 value &= ~PLLE_BASE_ENABLE_CML; 728 value &= ~PLLE_BASE_ENABLE; 729 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 730 731 /* clear lock enable and setup field */ 732 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 733 value &= ~PLLE_MISC_LOCK_ENABLE; 734 value &= ~PLLE_MISC_SETUP_BASE(0xffff); 735 value &= ~PLLE_MISC_SETUP_EXT(0x3); 736 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 737 738 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 739 if ((value & PLLE_MISC_PLL_READY) == 0) { 740 err = tegra_plle_train(); 741 if (err < 0) { 742 pr_err("failed to train PLLE: %d", err); 743 return err; 744 } 745 } 746 747 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 748 value |= PLLE_MISC_SETUP_BASE(0x7); 749 value |= PLLE_MISC_LOCK_ENABLE; 750 value |= PLLE_MISC_SETUP_EXT(0); 751 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 752 753 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 754 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 755 PLLE_SS_CNTL_BYPASS_SS; 756 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 757 758 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 759 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; 760 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 761 762 do { 763 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 764 if (value & PLLE_MISC_LOCK) 765 break; 766 767 udelay(2); 768 } while (--timeout); 769 770 if (timeout == 0) { 771 pr_err("timeout waiting for PLLE to lock"); 772 return -ETIMEDOUT; 773 } 774 775 udelay(50); 776 777 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 778 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f); 779 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18); 780 781 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 782 value |= PLLE_SS_CNTL_SSCINC(0x01); 783 784 value &= ~PLLE_SS_CNTL_SSCBYP; 785 value &= ~PLLE_SS_CNTL_INTERP_RESET; 786 value &= ~PLLE_SS_CNTL_BYPASS_SS; 787 788 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 789 value |= PLLE_SS_CNTL_SSCMAX(0x24); 790 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 791 792 return 0; 793} 794 795struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) 796{ 797 struct clk_rst_ctlr *clkrst = 798 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 799 800 switch (clkid) { 801 case CLOCK_ID_XCPU: 802 case CLOCK_ID_EPCI: 803 case CLOCK_ID_SFROM32KHZ: 804 return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; 805 default: 806 return NULL; 807 } 808} 809 810struct periph_clk_init periph_clk_init_table[] = { 811 { PERIPH_ID_SPI1, CLOCK_ID_PERIPH }, 812 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, 813 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, 814 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, 815 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, 816 { PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL }, 817 { PERIPH_ID_DISP1, CLOCK_ID_PERIPH }, 818 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, 819 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, 820 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, 821 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, 822 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, 823 { PERIPH_ID_PWM, CLOCK_ID_PERIPH }, 824 { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH }, 825 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, 826 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, 827 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, 828 { -1, }, 829}; 830