1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7/* Tegra AP (Application Processor) code */
8
9#include <common.h>
10#include <log.h>
11#include <linux/bug.h>
12#include <asm/io.h>
13#include <asm/arch/gp_padctrl.h>
14#include <asm/arch/mc.h>
15#include <asm/arch-tegra/ap.h>
16#include <asm/arch-tegra/clock.h>
17#include <asm/arch-tegra/fuse.h>
18#include <asm/arch-tegra/pmc.h>
19#include <asm/arch-tegra/scu.h>
20#include <asm/arch-tegra/tegra.h>
21#include <asm/arch-tegra/warmboot.h>
22
23int tegra_get_chip(void)
24{
25	int rev;
26	struct apb_misc_gp_ctlr *gp =
27		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
28
29	/*
30	 * This is undocumented, Chip ID is bits 15:8 of the register
31	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
32	 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
33	 */
34	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
35	debug("%s: CHIPID is 0x%02X\n", __func__, rev);
36
37	return rev;
38}
39
40int tegra_get_sku_info(void)
41{
42	int sku_id;
43	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
44
45	sku_id = readl(&fuse->sku_info) & 0xff;
46	debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
47
48	return sku_id;
49}
50
51int tegra_get_chip_sku(void)
52{
53	uint sku_id, chip_id;
54
55	chip_id = tegra_get_chip();
56	sku_id = tegra_get_sku_info();
57
58	switch (chip_id) {
59	case CHIPID_TEGRA20:
60		switch (sku_id) {
61		case SKU_ID_T20_7:
62		case SKU_ID_T20:
63			return TEGRA_SOC_T20;
64		case SKU_ID_T25SE:
65		case SKU_ID_AP25:
66		case SKU_ID_T25:
67		case SKU_ID_AP25E:
68		case SKU_ID_T25E:
69			return TEGRA_SOC_T25;
70		}
71		break;
72	case CHIPID_TEGRA30:
73		switch (sku_id) {
74		case SKU_ID_T33:
75		case SKU_ID_T30:
76		case SKU_ID_TM30MQS_P_A3:
77		default:
78			return TEGRA_SOC_T30;
79		}
80		break;
81	case CHIPID_TEGRA114:
82		switch (sku_id) {
83		case SKU_ID_T114_ENG:
84		case SKU_ID_T114_1:
85		default:
86			return TEGRA_SOC_T114;
87		}
88		break;
89	case CHIPID_TEGRA124:
90		switch (sku_id) {
91		case SKU_ID_T124_ENG:
92		default:
93			return TEGRA_SOC_T124;
94		}
95		break;
96	case CHIPID_TEGRA210:
97		switch (sku_id) {
98		case SKU_ID_T210_ENG:
99		default:
100			return TEGRA_SOC_T210;
101		}
102		break;
103	}
104
105	/* unknown chip/sku id */
106	printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
107		__func__, chip_id, sku_id);
108	return TEGRA_SOC_UNKNOWN;
109}
110
111#ifndef CONFIG_ARM64
112static void enable_scu(void)
113{
114	struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
115	u32 reg;
116
117	/* Only enable the SCU on T20/T25 */
118	if (tegra_get_chip() != CHIPID_TEGRA20)
119		return;
120
121	/* If SCU already setup/enabled, return */
122	if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
123		return;
124
125	/* Invalidate all ways for all processors */
126	writel(0xFFFF, &scu->scu_inv_all);
127
128	/* Enable SCU - bit 0 */
129	reg = readl(&scu->scu_ctrl);
130	reg |= SCU_CTRL_ENABLE;
131	writel(reg, &scu->scu_ctrl);
132}
133
134static u32 get_odmdata(void)
135{
136	/*
137	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
138	 * The BCT start and size are stored in the BIT in IRAM.
139	 * Read the data @ bct_start + (bct_size - 12). This works
140	 * on BCTs for currently supported SoCs, which are locked down.
141	 * If this changes in new chips, we can revisit this algorithm.
142	 */
143	unsigned long bct_start;
144	u32 odmdata;
145
146	bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
147	odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
148
149	return odmdata;
150}
151
152static void init_pmc_scratch(void)
153{
154	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
155	u32 odmdata;
156	int i;
157
158	/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
159#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
160	if (!tegra_cpu_is_non_secure())
161#endif
162	{
163		for (i = 0; i < 23; i++)
164			writel(0, &pmc->pmc_scratch1 + i);
165	}
166
167	/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
168	odmdata = get_odmdata();
169	writel(odmdata, &pmc->pmc_scratch20);
170}
171
172#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
173void protect_secure_section(void)
174{
175	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
176
177	/* Must be MB aligned */
178	BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
179	BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
180
181	writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
182	writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
183}
184#endif
185
186#if defined(CONFIG_ARMV7_NONSEC)
187static void smmu_flush(struct mc_ctlr *mc)
188{
189	(void)readl(&mc->mc_smmu_config);
190}
191
192static void smmu_enable(void)
193{
194	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
195	u32 value;
196
197	/*
198	 * Enable translation for all clients since access to this register
199	 * is restricted to TrustZone-secured requestors. The kernel will use
200	 * the per-SWGROUP enable bits to enable or disable translations.
201	 */
202	writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
203	writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
204	writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
205	writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
206
207	/*
208	 * Enable SMMU globally since access to this register is restricted
209	 * to TrustZone-secured requestors.
210	 */
211	value = readl(&mc->mc_smmu_config);
212	value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
213	writel(value, &mc->mc_smmu_config);
214
215	smmu_flush(mc);
216}
217#else
218static void smmu_enable(void)
219{
220}
221#endif
222
223void s_init(void)
224{
225	/* Init PMC scratch memory */
226	init_pmc_scratch();
227
228	enable_scu();
229
230	/* init the cache */
231	config_cache();
232
233	/* enable SMMU */
234	smmu_enable();
235}
236#endif
237