1/*
2 * sun50i H616 LPDDR4-2133 timings, as programmed by Allwinner's boot0
3 * for orangepi zero3 with the H618 and LPDDR4 memory.
4 *
5 * (C) Copyright 2023 Mikhail Kalashnikov <iuncuim@gmail.com>
6 *   Based on H6 DDR3 timings:
7 *   (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
8 *
9 * SPDX-License-Identifier:	GPL-2.0+
10 */
11
12#include <common.h>
13#include <asm/arch/dram.h>
14#include <asm/arch/cpu.h>
15
16void mctl_set_timing_params(const struct dram_para *para)
17{
18	struct sunxi_mctl_ctl_reg * const mctl_ctl =
19			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
20
21	u8 tccd		= 4;
22	u8 tfaw		= ns_to_t(40);
23	u8 trrd		= max(ns_to_t(10), 2);
24	u8 trcd		= max(ns_to_t(18), 2);
25	u8 trc		= ns_to_t(65);
26	u8 txp		= max(ns_to_t(8), 2);
27	u8 trtp		= max(ns_to_t(8), 4);
28	u8 trp		= ns_to_t(21);
29	u8 tras		= ns_to_t(42);
30	u16 trefi	= ns_to_t(3904) / 32;
31	u16 trfc	= ns_to_t(280);
32	u16 txsr	= ns_to_t(190);
33
34	u8 tmrw		= max(ns_to_t(14), 5);
35	u8 tmrd		= tmrw;
36	u8 tmod		= 12;
37	u8 tcke		= max(ns_to_t(15), 2);
38	u8 tcksrx	= max(ns_to_t(2), 2);
39	u8 tcksre	= max(ns_to_t(5), 2);
40	u8 tckesr	= tcke;
41	u8 trasmax	= (trefi * 9) / 32;
42	u8 txs		= 4;
43	u8 txsdll	= 16;
44	u8 txsabort	= 4;
45	u8 txsfast	= 4;
46	u8 tcl		= 10;
47	u8 tcwl		= 5;
48	u8 t_rdata_en	= 17;
49	u8 tphy_wrlat	= 5;
50
51	u8 twtp		= 24;
52	u8 twr2rd	= max(trrd, (u8)4) + 14;
53	u8 trd2wr	= (ns_to_t(4) + 17) - ns_to_t(1);
54
55	/* set DRAM timing */
56	writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
57	       &mctl_ctl->dramtmg[0]);
58	writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
59	writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
60	       &mctl_ctl->dramtmg[2]);
61	writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
62	writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
63	       &mctl_ctl->dramtmg[4]);
64	writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
65	       &mctl_ctl->dramtmg[5]);
66	/* Value suggested by ZynqMP manual and used by libdram */
67	writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
68	writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
69	       &mctl_ctl->dramtmg[8]);
70	writel(0x00020208, &mctl_ctl->dramtmg[9]);
71	writel(0xE0C05, &mctl_ctl->dramtmg[10]);
72	writel(0x440C021C, &mctl_ctl->dramtmg[11]);
73	writel(8, &mctl_ctl->dramtmg[12]);
74	writel(0xA100002, &mctl_ctl->dramtmg[13]);
75	writel(txsr, &mctl_ctl->dramtmg[14]);
76
77	clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x3f0);
78	writel(0x01f20000, &mctl_ctl->init[1]);
79	writel(0x00000d05, &mctl_ctl->init[2]);
80	writel(0, &mctl_ctl->dfimisc);
81	writel(0x0034001b, &mctl_ctl->init[3]);
82	writel(0x00330000, &mctl_ctl->init[4]);
83	writel(0x00040072, &mctl_ctl->init[6]);
84	writel(0x00240009, &mctl_ctl->init[7]);
85
86	clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
87
88	/* Configure DFI timing */
89	writel(tphy_wrlat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
90	       &mctl_ctl->dfitmg0);
91	writel(0x100202, &mctl_ctl->dfitmg1);
92
93	/* set refresh timing */
94	writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
95}
96