1/* 2 * sun50i H616 LPDDR3 timings, as programmed by Allwinner's boot0 3 * 4 * The chips are probably able to be driven by a faster clock, but boot0 5 * uses a more conservative timing (as usual). 6 * 7 * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> 8 * Based on H6 DDR3 timings: 9 * (C) Copyright 2018,2019 Arm Ltd. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#include <common.h> 15#include <asm/arch/dram.h> 16#include <asm/arch/cpu.h> 17 18void mctl_set_timing_params(const struct dram_para *para) 19{ 20 struct sunxi_mctl_ctl_reg * const mctl_ctl = 21 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 22 23 u8 tccd = 2; 24 u8 tfaw = ns_to_t(50); 25 u8 trrd = max(ns_to_t(6), 4); 26 u8 trcd = ns_to_t(24); 27 u8 trc = ns_to_t(70); 28 u8 txp = max(ns_to_t(8), 3); 29 u8 trtp = max(ns_to_t(8), 2); 30 u8 trp = ns_to_t(27); 31 u8 tras = ns_to_t(41); 32 u16 trefi = ns_to_t(7800) / 64; 33 u16 trfc = ns_to_t(210); 34 u16 txsr = 88; 35 36 u8 tmrw = 5; 37 u8 tmrd = 5; 38 u8 tmod = max(ns_to_t(15), 12); 39 u8 tcke = max(ns_to_t(6), 3); 40 u8 tcksrx = max(ns_to_t(12), 4); 41 u8 tcksre = max(ns_to_t(12), 4); 42 u8 tckesr = tcke + 2; 43 u8 trasmax = (para->clk / 2) / 16; 44 u8 txs = ns_to_t(360) / 32; 45 u8 txsdll = 16; 46 u8 txsabort = 4; 47 u8 txsfast = 4; 48 u8 tcl = 7; 49 u8 tcwl = 4; 50 u8 t_rdata_en = 12; 51 u8 t_wr_lat = 6; 52 53 u8 twtp = 16; 54 u8 twr2rd = trtp + 9; 55 u8 trd2wr = 13; 56 57 /* DRAM timing grabbed from tvbox with LPDDR3 memory */ 58 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, 59 &mctl_ctl->dramtmg[0]); 60 writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); 61 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, 62 &mctl_ctl->dramtmg[2]); 63 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); 64 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, 65 &mctl_ctl->dramtmg[4]); 66 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, 67 &mctl_ctl->dramtmg[5]); 68 /* Value suggested by ZynqMP manual and used by libdram */ 69 writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); 70 writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, 71 &mctl_ctl->dramtmg[8]); 72 writel(0x00020208, &mctl_ctl->dramtmg[9]); 73 writel(0xE0C05, &mctl_ctl->dramtmg[10]); 74 writel(0x440C021C, &mctl_ctl->dramtmg[11]); 75 writel(8, &mctl_ctl->dramtmg[12]); 76 writel(0xA100002, &mctl_ctl->dramtmg[13]); 77 writel(txsr, &mctl_ctl->dramtmg[14]); 78 79 writel(0x4f0112, &mctl_ctl->init[0]); 80 writel(0x420000, &mctl_ctl->init[1]); 81 writel(0xd05, &mctl_ctl->init[2]); 82 writel(0x83001c, &mctl_ctl->init[3]); 83 writel(0x00010000, &mctl_ctl->init[4]); 84 85 writel(0, &mctl_ctl->dfimisc); 86 clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); 87 88 /* Configure DFI timing */ 89 writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000, 90 &mctl_ctl->dfitmg0); 91 writel(0x100202, &mctl_ctl->dfitmg1); 92 93 /* set refresh timing */ 94 writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); 95} 96